Palo Alto, California, United States
R&D Executive and Technology Innovation Strategist, with world-wide recognition in Electronic Design and Semiconductor IC Fabrication. Fellow of the SPIE (Society for Applied Optical Science and Photonics). Pioneered the introduction of Machine Learning tools and Neural Network computations for VLSI CAD and IC Semiconductor Process Manufacturing, leading technical innovation from the last AI winter into today’s Deep Learning and Generative-AI renaissance. What's Next: “Make neural networks ‘uncool’ again …” (as in the motto of fast.ai): by inventing, developing, and deploying enterprise-grade Integrated Circuit Design Co-Pilots and CAD flows Optimization Assistants; by enabling Generative-AI synergies in customers’ verticals; by focusing on productivity amplification of end-user applications; by leading the transformation in IC Design, Electronic Design Automation, and advanced Semiconductor Manufacturing. -------------------------------------------------------------------------------------------- Career Highlights: + CTO @Motivo.ai + Design Enablement Fellow at GlobalFoundries + Director of DFM/CAD and Engineering R&D Fellow at GlobalFoundries, coordinating DFM R&D from 45 and 32/28nm, down to the next generations of 20 and 14nm technology nodes. + R&D Fellow at AMD, focusing on advanced Resolution Enhancement Technologies (RET), Optical Proximity Correction (OPC) and Design For Manufacturability (DFM) for 45 nm, 32 nm and 22 nm Technology Nodes. -------------------------------------------------------------------------------------------- Technical Areas: Physical design implementation and verification, Computational Lithography and Process Modeling, CAD and Electronic Design Automation (EDA).
Evolving Electronic Design Automation for the Generative AI Era
Data Analytics, Machine Learning, AI, Applied Algorithmic Intelligence