Austin, Texas, United States
Electrical Engineer with a passion for product development, physics, and semiconductor devices. Over ten years of semiconductor industry experience working on cutting-edge technologies, centered on product development, silicon characterization, product debug, silicon reliability, and data analysis. Highly adaptable to fast changing engineering needs, with a particular focus on driving complex problems to resolution.
Member of the EPYC Server organization as a System Level Test (SLT) Engineer. Main responsibilities and tasks performed: • Led the SLT efforts for the EPYC™ Bergamo (Zen 4c) line of products. Responsible for all characterization activities, test program development, and quality improvements, from New Product Introduction to Initial Production. Achieved 96% test program yield at IP milestone. • Executed on product development efforts for the upcoming EPYC™ Turin (Zen 5c). Responsible for silicon characterization and DPPM reduction efforts. Achieved less than 1000 DPPM before initial production lock-in. Additional focus on exploratory characterization, resulting in test program increased diagnostic coverage. • Responsible for major debug activities with significant impact on yield (10%+ pareto items). Maintained triage, design of experiment, and time to item resolution within a month. Offered extended debug support during Product Sustaining phase. • Constant communication with adjacent teams, maintaining alignment and providing feedback between Platform, ATE, BIOS, Diagnostics, HW Development, and Silicon Design. • Training, mentoring and continuous guidance of junior engineers. Responsible for implementing guidelines on characterization code development and data collection best practices.
Delivered to market the X100 NVMe SSD, based on 3DXPoint™ memory technology. Main responsibilities and tasks performed: • Electrical characterization of the memory array across three technology generations, from single memory cell test structures to packaged dies. • Developed customized Python code running ATPG patterns for failure mechanisms testing (write endurance. read endurance, thermal disturb, retention). • Correlation activity and data mining between ATE (die level failures and performance), Probe (die binning), and Wafer Level Reliability (extended time test). • Close collaboration with SLT, Yield Enhancement and Process Integration teams, supporting product enablement activities. • Owner of a key meeting, tasked with identifying major roadmap blockers, and driving their resolution.