Georgetown, Texas, United States
Principle System Engineer with a focus on enabling emerging innovative uses of leading edge acceleration technologies and innovative scale out AI Supercomputers. Particularly interested in HPC and machine learning solutions and visualization in concert with GPU accelerated clusters (x86 and POWER). Significant background in High Performance Computing, IBM POWER technology both CPU architecture and system design and simulation. In depth knowledge of I/O technologies including PCIe and InfiniBand and high performance storage design. Specialties: System architecture, large scale cluster design for HPC and AI, performance evaluation of technologies, competitve evaluation, AIX/Linux admin, Cluster software technologies
After working many years building Supercomputer transmissions, suspensions and race tracks to run these amazing compute engines, now planning to fully use them :)
- Architect and deploy large scale GPU based AI Supercomputers using emerging technology - Collaborate on unique next generation system interconnect and network design - Drive unique technology proof of concepts focused on function, performance and data center usability
Enablement of emerging use cases for NVIDIA technologies - GPU Solutions architecture - Performance modeling - Benchmarking - Client education for solution design and software stack - Liaison between clients and development teams
Architecting Supercomputers for National labs based on POWER and x86 technologies. - Focus on high performance computing and clustering. - Evaluate and answer request for proposals from Federal clients. Requires expertise in all areas of system design from CPU details like pipeline and cache design and operation to I/O interconnect to physical/install design for power/cooling/space to compilers/HPC codes to workload management and other clustering tools.
Lead team to bring up PowerPC CPUs and support chips developing and driving system simulation plans with a focus on function, performance and power useage.
Chief system architect for IBM Power server products - Developed system vision for new POWER5 based server family working with research, processor development, operating systems and marketing teams. Formed the initial product designs for 2003 product launch. - Merged the iSeries and pSeries structures using a building block approach and common structures from top to bottom to reduce firmware/OS complexity and enable IBM's Virtualization Engine. - Worked with technical support teams ranging from CPU, to Asics to firmware to OS (AIX/iOS) to packaging design in developing final solution. - Power technology evangelist participating in briefing center and on several onsite customer calls (Ericsson, Group Bull, etc.) focusing on Telco and HPC applications. - Codeveloped PowerPC based blades strategy for use in the IBM BladeCenter infrastructure. Developed initial proposal starting with strategic need to gathering input from inside and outside IBM. Developed a strategic roadmap and drove technical issue resolution during development.
Formed new systems design team to support the future product development Led team to create POWER4 system designs and workbooks in support of Gigaprocessor product family launch in 2001.
Managed a 12 person to team in developing and shipping the highend RS/6000 PowerPC 604 2 way workstation from schematic to lab verification to general availability.
As part of the IBM Power Personal Systems effort with Apple and Motorola, generated the designs for multiple RS/6000 PowerPC products and lead teams in their implementation from logic/system design to lab bringup/debug to GA. - PowerPC 603 "Polo" prototype executive desktop product for Power Person Systems - PowerPC 604 "Tiger" RS/6000 (43P) Workstation desktop/tower - PowerPC 604 "Tiger II" RS/6000 (43P Model 150) Workstation desktop/tower - Presented products in customer briefings, participated at customer sites in benchmarking and demonstrations - Involved all aspects of system design from logic design to schematic entry to board layout to bringup and test. Involved heavily in lab debug in addition to AIX issues during test.