Lorenzo Gerosa

Analog IC Designer Manager

Desio, Lombardy, Italy

About

Experience

  • STMicroelectronics (19 yrs 6 mos)
    • IC Analog Design Manager
      Oct 2019 - Present · 6 yrs 10 mos

      Analog team manager, mainly focused on High Speed Serial Interfaces. Main activities on 56Gbps/112Gbps Serdes design, layout and validation with latest finfet technologies. Driver and TIA in advanced BiCMOS technologies for silicon photonic integration. Electronic for quantum computing

    • Analog IC designer
      Feb 2007 - Oct 2019 · 12 yrs 9 mos

      Design of analog IC in CCI - Data Storage Division for HD RW-channel. ADC, PLL and CTLE for 1Gbps/10Gbps Ethernet. Clock generation and distribution for 200Gbps transceiver in Silicon Photonics. Transceiver design for 56Gbps in advanced Finfet technologies.