Kaohsiung Metropolitan Area
Devoted in Signal Integrity and Power Integrity (SI/PI) Engineer with extensive experience in high-speed digital design and advanced semiconductor integration. My expertise lies in optimizing the electrical performance of next-generation architectures, specifically focusing on chiplet interconnects, 3D packaging technologies, and ultra-high-speed data transmission standards. I have a proven track record of managing complex simulation workflows and routing methodologies to ensure robust system performance across diverse hardware platforms platforms. Technical Core Competencies • TSMC Advanced Packaging Expertise: Proficient in design and simulation for CoWoS-S, CoWoS-R, CoWoS-L, and InFO architectures, including specialized knowledge in SoW-X (System-on-Wafer) technology. • UCIe Protocol Implementation: Extensive experience with UCIe-A (Advanced) and UCIe-S (Standard) implementations, covering the evolution of data rates from 16 Gbps to 64 Gbps. • Next-Generation Memory Integration: Skilled in the SI/PI design and PDN optimization for HBM3, HBM4, and HBM4E high-bandwidth memory stacks. • Ultra-High-Speed SerDes: Advanced capability in managing channel loss and impedance control for SerDes interfaces reaching up to 224G per lane. • PCIe Gen 7 Development: Early-stage adoption and design validation for PCIe 7.0 (128 GT/s) standards, ensuring compliance with rigorous PAM4 signaling requirements. • Substrate & RDL Routing: Expert in FSRDL (Front-Side) and BSRDL (Back-Side) routing methodologies for complex multi-die interconnections. • Advanced Simulation Workflows: Utilizing industry-standard tools (such as Ansys HFSS, SIwave, or Cadence Sigrity) for full-wave extraction and time-domain analysis. • High-Speed Interconnect Optimization: Specializing in impedance matching (88–93 ohm targets) and minimizing insertion loss (targeting 0.25dB/mm) for long-reach main routing. • 3D Stacking PDN Design: Developing robust Power Delivery Networks for 3D-stacked configurations, including SoC and memory integration (DRAM-on-SoC). • Physical Architecture Validation: Bridging the gap between conceptual silicon architecture and physical package implementation to achieve maximum bandwidth density. Professional Highlights • DAC 2026 Participant: Selected as a poster presenter for the 63rd Design Automation Conference (DAC), showcasing innovations in semiconductor desig
Devoted in Signal Integrity and Power Integrity (SI/PI) Engineer with extensive experience in high-speed digital design and advanced semiconductor integration. My expertise lies in optimizing the electrical performance of next-generation architectures, specifically focusing on chiplet interconnects, 3D packaging technologies, and ultra-high-speed data transmission standards. I have a proven track record of managing complex simulation workflows and routing methodologies to ensure robust system performance across diverse hardware platforms. Technical Core Competencies • TSMC Advanced Packaging Expertise: Proficient in design and simulation for CoWoS-S, CoWoS-R, CoWoS-L, and InFO architectures, including specialized knowledge in SoW-X (System-on-Wafer) technology. • UCIe Protocol Implementation: Extensive experience with UCIe-A (Advanced) and UCIe-S (Standard) implementations, covering the evolution of data rates from 16 Gbps to 64 Gbps. • Next-Generation Memory Integration: Skilled in the SI/PI design and PDN optimization for HBM3, HBM4, and HBM4E high-bandwidth memory stacks. • Ultra-High-Speed SerDes: Advanced capability in managing channel loss and impedance control for SerDes interfaces reaching up to 224G per lane. • PCIe Gen 7 Development: Early-stage adoption and design validation for PCIe 7.0 (128 GT/s) standards, ensuring compliance with rigorous PAM4 signaling requirements. • Substrate & RDL Routing: Expert in FSRDL (Front-Side) and BSRDL (Back-Side) routing methodologies for complex multi-die interconnections. • Advanced Simulation Workflows: Utilizing industry-standard tools (such as Ansys HFSS, SIwave, or Cadence Sigrity) for full-wave extraction and time-domain analysis. • High-Speed Interconnect Optimization: Specializing in impedance matching (88–93 ohm targets) and minimizing insertion loss (target 0.25dB/mm) • 3D Stacking PDN Design: Developing robust Power Delivery Networks for 3D-stacked configurations, including SoC and memory integration