Kanpur, Uttar Pradesh, India
I'm Kuldeep Kumar, a final-year Dual-Degree (B.Tech-M.Tech) student in Electrical Engineering (VLSI) at IIT Kanpur, driven by a passion for semiconductor R&D, device modeling and analog/VLSI circuit design. I strive to bridge academic theory with practical innovation in electronics. Research: My master’s thesis investigates Gate-Induced Drain Leakage (GIDL) in nanowire junctionless FETs. I'm using Sentaurus TCAD simulations and custom Verilog-A models (with SPICE validation) to understand and mitigate leakage in these advanced transistors. This research has deepened my understanding of device physics and its impact on circuits. Projects & Skills: Beyond my thesis, I've worked on diverse projects that refined my technical skills- 1. LUT-based FDSOI Modeling: Developed a LUT-based Verilog-A model for fully-depleted SOI (FD-SOI) MOSFETs to improve circuit simulation accuracy. 2. Analog Circuit Design: Designed differential amplifier using Cadence, sharpening my analog design expertise. 3. Process Reverse Engineering: Reverse-engineered a p-channel MOSFET fabrication process to link process parameters with device performance. 4. Device Characterization: Extracted BSIM4 parameters with Keysight IC-CAP to create precise transistor models for SPICE.Through these projects, I've become proficient with industry-standard tools like Cadence, Sentaurus TCAD, Verilog-A, MATLAB and IC-CAP. Academic Excellence: I've maintained a CPI of 9.2/10 in my M.Tech (VLSI) and qualified GATE 2024 & 2025 - reflecting a strong grasp of fundamentals and a commitment to continuous learning. Serving as a Teaching Assistant for a Digital Electronics course helped reinforce my core knowledge while mentoring undergraduate students.Leadership & Outreach: I served as President of Hall IX and Overall Head of the Electrical Engineering Association, where I honed leadership and team-building skills. I was also the Athletics Coordinator, promoting a healthy balance between academics and sports. Beyond campus, I mentor JEE aspirants and lead educational initiatives with the Anany Pahal Foundation to inspire aspirants. Looking Ahead: As I approach graduation, I'm excited to apply my skills in the professional world. I'm targeting roles in semiconductor R&D, device modeling or analog/VLSI circuit design where I can contribute to advanced projects and keep learning. If you share my enthusiasm for semiconductors or have opportunities in this space, let's connect - I'd love to collaborate and make an impact together.