Stuttgart Region
Ph.D.-trained Semiconductor R&D engineer with strong expertise in thin-film process development, wafer-level characterization, reliability analysis, and process integration. Experienced in driving material and tool innovation, designing experiments (DOE), identifying root causes through failure analysis, and translating characterization data into process optimization and yield improvement in foundry-like environments. Combines hands-on fab experience, simulation and data-analysis capability, and international research training to develop scalable semiconductor technologies.
Engineering department: Sensor Process Technology - Spearheading pathfinding for novel piezoelectric thin films, driving material characterization, patent creation and surveillance, and external collaborations with suppliers and research institutes. Led material integration and test-vehicle processing/characterization, managing contamination clearance and demo-device layout design and fabrication. - Partnering with suppliers to co-develop an in-line parallel lifetime characterization tool, implementing process qualification flows and defining lifetime specification. Led machine spec definition, acceptance, and Fab integration. Reduced reliability data acquisition time from months to hours and accelerated sputtering DoE optimizations. - Led foundry technical focus teams to resolve piezo-stack integration issues. Leveraged failure analysis (FA) and problem-solving techniques to identify root causes, achieving a 10-fold increase in customer product lifetime. - Developed a Convolutional Neural Network (CNN) for image recognition to track laser position drift in a Double Beam Laser Interferometer (DBLI), reducing measurement error by 5%. - Architected a data evaluation pipeline integrating in-line defect data, Automated Optical Inspection (AOI), and wafer-level testing to trace breakdown root causes and drive yield enhancement.
Engineering department: Sensor Process Technology - Identified reliability degradation mechanisms and key crystallographic defects in novel piezoelectric thin films (PZT, KNN) to establish lifetime prediction models for piezoMEMS. - Implemented wafer-level defect detection technologies to quantify deposition quality and monitor thin-film lifetime. - Executed DoE to optimize piezo-stack lifetime, achieving a 2-fold lifetime increase under Highly Accelerated Lifetime Testing (HALT). - Engineered customized piezoelectric characterization setups to accelerate piezoMEMS foundry process development and qualification.
Global development and quality - Directed the pre-development project "Design of High-Mobility III-V Epitaxial Stacks" for next-generation high-sensitivity Hall magnetic sensors. - Executed semiconductor device modeling and simulation to optimize electrical parameters, proposing stack designs that achieved a 5-fold sensitivity improvement while meeting noise, thermal drift, and current consumption specifications.
300mm wafer facility department - Proposed optimizations to the automatic titration and replenishment system to improve accuracy in monitoring H2O2 concentration in slurry used in chemical-mechanical polishing (CMP) process.