Koen Verheyen

Analog Design Engineer bij ams AG

Ghent Metropolitan Area

About

Experienced in CMOS image sensors, power management, and high-speed circuit design. Skilled in analog circuit design, top-level mixed-mode simulation, and behavioral modeling. Passionate about research and development, with a growing focus on system-level thinking, integration, and architectural design. Aspiring to transition into a Chip Architect or System Architect role to drive innovation at a higher level.

Experience

  • ams AG (6 yrs 4 mos)
    • Staff Engineer, R&D Analog Design
      Jul 2024 - Present · 2 yrs 1 mo

    • Senior Engineer, R&D Analog Design
      Jan 2022 - Jul 2024 · 2 yrs 7 mos

    • Engineer, R&D Analog Design
      Apr 2020 - Dec 2022 · 2 yrs 9 mos

      Joined the CMOS image sensor group, contributing to analog design across multiple chips, with a focus on LDOs. Performed top-level mixed-mode simulations and developed models for analog circuits to accelerate simulations and enable model vs. schematic validation.

  • onsemi ()
    • Senior Analog Design Engineer
      Apr 2020 - Apr 2020 · 1 mo

    • Analog Design Engineer
      Nov 2016 - Apr 2020 · 3 yrs 6 mos

      Designed analog circuits, performed top-level mixed-mode simulations for verification, and characterized devices in the lab, correlating measurements with ATE results. Circuit experience: Thermal shutdown circuit, current reference, R-2R ladder DAC, LDO, bandgap, oscillator, POR, switching converter Supervised an intern during the summer of 2017.

  • Co-founder & hardware lead at Pozyx Labs
    Mar 2015 - Nov 2016 · 1 yr 9 mos

    Designed and developed the hardware for an indoor and outdoor positioning platform compatible with Arduino. Responsible for PCB layout, prototyping, soldering, and supporting batch production

  • Researcher at Ghent University
    Aug 2011 - Nov 2016 · 5 yrs 4 mos

    Conducted research in high-speed and high-frequency electronic circuits. Primary research focus was digital PLLs. Worked on behavioral modeling, top-down design, high-speed CMOS, sigma-delta modulation, and transmission line filters. Additionally, supervised student groups for their bachelor projects and performed logic synthesis and place & route for simple digital logic blocks.

  • Visiting researcher at EPFL (École polytechnique fédérale de Lausanne)
    Oct 2015 - Dec 2015 · 3 mos