Cary, North Carolina, United States
• Collaborate with design and verification teams to plan the verification strategy for the given IPs. This includes defining verification goals, scope, methodologies, and metrics for measuring effectiveness and vertical scalability. • Developed and executed verification plans for the IP in the complex designs. Estimate the time for each task and that helps upper management to decide resource planning. • Created and maintained System Verilog/UVM testbenches for functional verification, including testcase development, sequences, drivers, monitors, scoreboard, and verification environment. • Develop assertions and properties to specify and check desired behaviors, constraints, and invariants withing the design. Assertion helps to detect violations of the design intent and facilitate debugging by providing clear failure messages. • Analyze functional coverage metrics, code coverage and toggle coverage to ensure that verification environment exercises all aspects of the design, including statements, branches, conditions, and expression. This helps to identify untested or unreachable code. • Implemented and optimized constrained-random test environments to improve verification coverage, identify corner-case scenarios and fill the coverage holes. • In multiple time zones, collaborated with design teams to identify and debug RTL issues, ensuring design correctness and functionality. File the JIRA to track and resolve the bugs. • Worked closely with cross-functional teams including design, architecture, and software to debug, resolve issues and meet project milestones and deadlines. • Mentor junior verification engineers and interns, sharing my expertise and best practices in ASIC design verification. Participate in knowledge-sharing activities within the team.
Delivering Lectures Course Planning and Curriculum Design Grading and Assessment Managing Classrooms Attendance Records Course Management