San Francisco Bay Area
Work in performance modeling and analysis of the core CPU.
Developed architectural model of the x86 - AMD64 instruction set architecture in the form of an execution driven simulator with a focus on the virtualization instructions. Additionally, worked for a short time on a random test generator.
Ran the Spec 2006 on new architectural models looking for weaknesses. Investigated short branches that might be converted into predicated branches by the hardware without software support.
Worked on analyzing Fortran kernels for store-to-load forwarding and prefetching on the Power5 processor. Also, made compiler optimization recommendations.
Floating point logic (RTL) designer for Power4, Power5, and PowerPC 970 microprocessors. Designed the power gating scheme for the Power5/PPC 970 floating point unit. Power designs were previously not power gated.