United States
Experienced hardware engineer with over 20 years in the semiconductor industry, specializing in DFT methodology and ASIC verification. Skilled in RTL design, MBIST development, and silicon bring-up, with a strong focus on improving chip quality and test efficiency. Passionate about solving complex technical challenges through collaboration and continuous innovation
Responsible for MBIST RTL design and insertion flow developmentProvided ASIC DFT methodology optimization to support high-performance chip testing and verificationCollaborated closely with RTL, verification, and silicon teams to improve structural and functional RAM testing flows
Focused on ASIC DFT, including MBIST design, verification, and silicon bring-upDeveloped MBIST engines targeting SRAM, DRAM, and customized RAMsImproved test flows to narrow the gap between structural RAM tests and functional tests, enhancing network chip reliability
Experienced hardware development engineer with a strong background in ASIC design, verification, and testing. Skilled in developing high-performance, reliable hardware solutions through efficient design practices and cross-functional collaboration
Responsible for ASIC functional verification and silicon testing,Assisted in test planning and experimental data analysis,Learned and applied DFT testing methodologies to enhance chip reliability