Keith Flynn

Manager Feol (Front end of line) Process Integration

Dresden, Saxony, Germany

About

CMOS, Technology Transfer, Lean Six Sigma, Black Belt, Thin-Film Solar, CIGS, Semiconductors, Taiwan, Germany, Ireland, Asia, English, German, Chinese language skills, FAS Overseas Graduate Program

Experience

  • GLOBALFOUNDRIES (15 yrs 6 mos)
    • Manager Feol (Front end of line) Process Integration
      Apr 2015 - Present · 11 yrs 3 mos

      Feol defectivity reduction, transistor variability reduction.

    • Senior Section Manager Feol (Front end of line) Process Integration
      Nov 2013 - Mar 2015 · 1 yr 5 mos

    • MTS Technology & Integration
      Jan 2011 - Oct 2013 · 2 yrs 10 mos

      Jan 2011 - July 2012 Overall Integrator for a 45nm Bulk technology. July 2012 - Overall Integrator for a 28nm Bulk technology transfer

  • Senior Project Manager Process Transfer at Bosch Solar CISTech GmbH
    Jun 2009 - Jan 2011 · 1 yr 8 mos

    Transfer and ramp-up of a thin-film (CIGS) photovoltaic process from the reference site in Brandenburg in Germany to a licensee (Sunvim Solar Technology) in Gaomi, Shandong Province, China. Processes transferred include Sputter (Molybdenum, iZnO, ZAO), Scribe (Laser and mechanical), Diffusion, Chemical Bath/CBD (CdS) and Backend.

  • Process Integration Module Leader DRAM Technology Transfer at Qimonda, Dresden, Germany
    Dec 2003 - Apr 2009 · 5 yrs 5 mos

    Responsible for the Transfer and Synchronsiation of FEOL (DT: Deep Trench and STI: Shallow Trench Isolation) and BEOL Process Modules (SC: Stacked Capacitor) from Germany to other Qimonda sites in the US , joint-ventures (Inotera memories, Taiwan) and foundries (SMIC, China and Winbond Electronics, Taiwan)

  • Development Engineer at Vishay
    Jul 2000 - Nov 2003 · 3 yrs 5 mos

    Development engineer respsonsible for the development of IPADs (Integrated Passive Active Devices), low voltage Zener diodes, ESD Array devices, Bi-directional Thyristors (Triacs). Project Leader for the development of a small outline SMT package (SOD523) together with Vishay sites in Heilbronn, Germany and Vöcklabrück, Austria.

  • Process Engineer at General Semiconductor
    Sep 1997 - Jun 2000 · 2 yrs 10 mos

    Diffusion Process engineer responsible for development and sustaining of Poly processes (SIPOS - Semi Insulating POly Silicon).