Noida, Uttar Pradesh, India
I am a VLSI Design Engineer specializing in Backend implementation flows, with hands-on experience across Synthesis, Static Timing Analysis (STA), Power Analysis, Physical Design concepts, and RTL sign-off methodologies. My goal is to keep deepening my expertise in STA, synthesis methodologies, physical design fundamentals, and industry sign-off flows to contribute to high-performance silicon development.
Worked as Synthesis & STA engineer. Performed RTL to gate-level synthesis using tools like Genus, targeting optimal PPA. Developed and refined SDC constraints for clocks, I0 delays, false paths, and multicycle paths. Conducted multi-mode multi-corner (MMMC) synthesis and timing signoff for complex SoCs. Analyzed post-synthesis reports to debug timing violations. Ran STA using Prime Time, identifying and resolving Timing violations Ensured logical equivalence (LEC) between RTL and synthesized netlist using tools like Conformal. Worked closely with Physical Design, RTL, and DFT teams to maintain timing closure across PPA (Power, Performance, Area) goals. Performed low-power synthesis using UPF/CPF, ensuring correct implementation of power domains, isolation cells, level shifters, and retention strategies. Conducted low-power checks for power domain crossings, missing isolation rules, and retention flop coverage. Reviewed critical path reports, timing exceptions, and cell utilization for performance bottlenecks. Delivered clean, constraint-compliant netlists for physical implementation and signoff.
The summer internship at Oil and Natural Gas Corporation (ONGC) provided a valuable opportunity to work on IP Protocols
I gained proficiency in Verilog, a hardware description language used for designing digital circuits in FPGA and ASIC.
During my training in PINE i completed Hardware System Design using Schematics Design and its Implementation on FPGA Nexys A7 Board.