Poing, Bavaria, Germany
System Software Architect for an Intel Internal Semiconductor test-system (ATE). Implemented multiple major SW features which required coordination between HW, FPGA and SW teams. Established Requirements driven approach for specifying new features, Established a high-performing new SW development and validation team in India within two years. Successfully collaborating with geo-diverse teams across multiple time-zones. Strong Technical Leadership with great communication skills, in-depth knowledge of semiconductor test (Digital/Analog/RF/Memory) and DFT, strong Software development background in multiple programming languages (C++, Java, Matlab) and great analytical and problem solving skills. Driving innovative solutions, always questioning the status-quo.
• Lead System Software Architect for an international (US/India/Malaysia) software and validation team of 75 people developing HDMT, a semiconductor high-volume manufacturing test system. • Alignment of SW features with customers. • Established long-term tester SW vision and road map. • Drove implementation of multiple major SW features from definition to on-time, in-budget delivery with high quality. • Realized more comprehensive product and api documentation based on requirement documents. • Directed the implementation of an IDE for the tester software. • Technical management of external contract workers and suppliers. • Implementation of secure development life-cycle practices. • Enabling of real-time data-streaming of semiconductor test-results to facilitate AI model based decision making. • Mentoring and development of multiple engineers into leadership roles.
• Technical management/Product Owner of a newly setup SW Development and Validation Team in India (25 people) for a burn-in test system • Developed a high performing team within two years, delivering twelve SW releases on time in 2022 • Two major new features implemented in 2022 • Implemented requirements driven approach to develop new features • Hiring, training, coaching and support of India team members, mentoring of managers and senior developers • Worked with multiple internal customers to define requirements for new features • In depth understanding of test-engineer use-models (internal to Intel and external) • Significant contributions to the long-term tester SW vision and road map • Drove changes to Usability, Architecture and CI setup of the tester SW • Transitioned the tester SW code-base to Visual Studio 2022 and C++20 • Introduced conan package management for providing third-party dependencies • Created Proof-of-concept for transitioning build system from msbuild to CMake • Created Proof-of-concept for using Sphinx to create unified SW and API documentation • Competitive bench-marking against external tester SW
• Product Owner of a 5 person SW-Team which is located in Malaysia • Bring-up of a completely new SCRUM team • Training and Support of the Team members • Planning, Feature definition and Code-Review • Awareness of cultural differences due to the different geo-graphical location • Individual contributor to the ATE SW development (improved pattern modification and load speed) • Defined/Aligned required HW/SW features for enabling efficient RF testing on next generation RF Instrument • Improved internal demodulation library for 5G/NR • Implemented RF Verification tooling (automated measurement of EVM performance of different bench-top instruments) • Definition and Prototyping of Spectrum-Analyzer/Signal-Generator/Demodulation GUIs • Defined and simulated RF data-path using Simulink, checked feasibility of FPGA implementation
• System-Engineer for an airbag control unit with integrated vehicle dynamics sensor cluster. – Analysis of Customer requirements – Creation of the system specification. – Creation of the system architecture taking into account functional safety considerations. – Alignment of the sensor cluster requirements between ESP and Airbag ECU – Coordination of the System-Test. • Characterization of the vehicle dynamics sensor cluster: – Creation of the test-specification and reports. – Conception and execution of lab and driving campaigns to evaluate sensor performance. – Presentation of the results at the customer. – Supporting the test-activities at the customer. • Communication and Coordination with customers and suppliers. • Resident Engineer at BMW Munich.
• Project Lead for the development of an electric motor simulator (Hardware, Software and VHDL) used in the verification of inverters. • Responsible for 10 employees. • Project management and controlling. • System-Engineering: Creation of the System-Architecture and derived specifications. • Configuration- and Change-management. • Communication and Coordination with the customers. • Tender preparation, calculation and customer presentation. • Quality-management according to ISO 9001/EN9100. • Process documentation. • Development according to the V-Model, DO-178, DO-254. • Two articles covering Real-Time simulation of electric motors in ATZelektronik 01/2010 and Hanser Automotive 10/2010 • Multiple presentations at conferences and workshops
Working as Test program development engineer for DRAM memory chips on Advantest memory test systems. • Responsible test program engineer for a 70 nm DDR2 memory chip. • Implementation of an e-fuse qualification program for all products. • Drove discussion and implementation of a new test program development structure (introduction of a new version control system, new build system, regression testing). • Developed characterization test-program to reduce the time spent for design analysis by automatically verifying the functionality of the test modes implemented on a DRAM memory chip. – Development of the necessary software in Java, C++ and Matlab. – Responsible for the test definition, implementation, execution and result evaluation. – Presentation of the results to the Design-Analysis team and the designers. – Continuous improvement of the test coverage – World-wide roll-out to all Development Centers. – Training and Support – Implementation on a high-speed wafer-level tester. – Functional Task Team Leader coordinating all implementation and development work done world-wide by eight engineers. • Detailed Knowledge of all DRAM interface protocols (SDR, DDR1/2/3, GDDR5, XDR and NMT). • Simulation of DRAM patterns in EPIC and VERILOG. • Definition of a xml-file format to exchange the Testmode specifications between Design and Test. Implemented XSLT style sheets for conversion into different formats. • Implementation of a Fail-Bitmap library and supporting tools. • Developed a tool for decoding various binary information which is read out from DRAM chips • Leading student trainees and mentoring new hires. • Participated as mentee in the mentoring program. • Intercultural Training China.