Sant Pere de Ribes, Catalonia, Spain
- Experience as FPGA / Embedded SW group leader and technical project manager in a structured JIRA/Scrum eSAFE environment. - FPGA/SoC design & verification engineer with experience in different segments (aerospace, avionics, maritime, medical, high performance computing and R&D). - Experience working with mission-critical HW development standards (DO-254, IEC61508 , ECCS (ESA) ) - Experience within all stages of an FPGA development cycle. From requirement capture , to architecture development ,implementation, verification to product release. Broad experience in product lifecycle and maintenance. - Experience with Hardware bring ups , characterization and as a hardware verification group leader. - Experience performing system design / product management tasks. - Experience with SoC from Xilinx (Zynq/Microblaze) and Altera (NIOS II), and with PIC16/32 uCs. - Competence developing test/control systems in Labview. Experience with Labview FPGA module. - Competence modeling physical systems (for instance, sonar propagation models) and real time DSP systems in MATLAB . - Experience within the following domains/applications : 1) Defense : Audio / (monochrome) video processing and radio comms (handheld & SATCOM) 2) Space : TM/TC designs and RF (High Data Rate transceivers) 3) Medical Ultrasound: both handheld and console based systems. Systems with up to 256 channels. 4) Sonar : CHIRP based Echosounders and Doppler speed logs for navigation. 5) Safety systems: industrial comm protocols implemented in SIL3 , SIL4 systems (maritime, offshore) 6) R+D : Electro-optics & quantum information domain. 7) High Performance Computing and Cache Coherency.
Complex DSP algorithm implementation on FPGAs for RF designs. Hardware test setup development. Responsible for HW verification setups.
Hardware & FPGA engineer for handheld medical ultrasound products. Main responsibilities: 1) Implementation of time critical designs on Lattice FPGAs (MachXO2/XO3) 2) Hardware bring ups, characterization and formal verification.
Main responsibilities: 1) System Architect and lead developer for new generation CHIRP dual frequency band echosounders. 2) Implementing DSP algorithms on FPGAs for navigational Doppler Speed loggers and Echosounders. 3) HW integration testing. 4) Design of automated test setups for production.