Eindhoven, North Brabant, Netherlands
I’m a principal digital verification engineer with over 23 years of experience, working in multi-cultural, multi-site and multi-disciplinary project teams. My broad experience enables to execute and drive verification activities at block and chip level and lead verification teams. I’m very quality minded, striving for high quality first-time-right products. I'm a team player, flexible, eager to learn, pro-actively take up challenging assignments and enjoy supporting/coaching others. I have a clear and concise communication style.
BL - Secure Transactions and Identification Verification engineer for multiple next generation Smart Card ICs for banking and e-government. Responsible for verification of CPU, Memory Management Unit, Interrupt controller, Secure Control Block, Timers and Watchdog. Verification is done on blocklevel and integrated toplevel. In this period I also acted as backup verification lead.
Based in the Central R&D organization, mainly working for BU-ID (Identification) Digital Verification Lead for NXP VIP project (Project for NXP key customer). As verification lead I directly communicated with and reported to the customer.
System & Software Design Methodology specialist in the System Design Methodology group, part of Philips Semiconductors until Oct. 2006. From Oct. 2006 onwards part of NXP Semiconductors B.V. Besides technical knowledge, working on methodologies/flows also required good communication, presentation and documentation skills. 2011: Development of c++/SystemC-based transactor between a Software development environment and a SystemC-based virtual prototype of a NFC product. This transactor ensured a 6 months pull-in of HW-SW co-verification compared to RTL based HW-SW co-verification 2009 – 2011: Architect for High Level synthesis methodologies and SystemC-based modeling libraries. 2008: SystemC Transaction Level Modeling (TLM) specialist. 2004 – 2008: Competence specialist on C/C++/SystemC-based high level synthesis to Hardware implementation. 2002 – 2007: System & Software Design Environment flow Architect: Defined and Specified the SSDE flow architecture and related methodology. 2000 – 2001: System & Software Design (SSD) methodology specialist. Focus on Application dependent IC Architecture analysis.
1997 – 1999: Senior Specialist on parasitic extraction and static timing analysis methods for digital Integrated Circuit designs. - Applied methodology on several production designs. - Responsible for deployment of the methodology in the company (documentation/presentation). 1995 – 1996: Architect and digital designer of a single-chip, digital-oscilloscope processor with truly real-time image build up.