Bengaluru, Karnataka, India
I’m an ASIC Design Verification Engineer with over 4 years of experience in developing and executing advanced verification environments using SystemVerilog, UVM, and SVA. My expertise covers functional verification, coverage closure, regression testing, and debugging for complex SoC and RTL designs. I’ve contributed to automotive and semiconductor verification projects, ensuring high-quality deliverables and first-pass silicon success. Skilled in UVM-based methodologies, I focus on building reusable, scalable verification environments and collaborating across design and validation teams to ensure full verification closure. Passionate about ASIC RTL verification, I thrive on innovation, precision, and driving efficiency throughout the verification lifecycle. Always open to challenges that expand my technical depth and contribute to cutting-edge semiconductor solutions.
• ASIC Digital Design Verification Engineer with 4 years of experience in digital and formal verification for automotive-customized ICs • Proficient in SystemVerilog, VHDL, UVM, UVVM, and Siemens QuestaSIM • Skilled in assertion-based verification, property specification, and formal verification techniques for early bug detection • Experienced in developing and managing verification environments and ensuring coverage closure • Knowledgeable in ISO 26262 functional safety compliance for automotive designs • Collaborative team player working with global cross-functional teams and suppliers • Provides mentoring and technical guidance to junior engineers • Committed to achieving first-pass silicon success and continuous verification process improvement