Jitendra Bhandari

ML Engineer @ Synopsys

Sunnyvale, California, United States

About

I am a Ph.D. student in the Department of Electrical and Computer Engineering at New York University. I have joined NYU in the Fall'20. I had done my B. Tech at IIT Kharagpur, with a specialization in Instrumentation Engineering from the Electrical Engineering Department, graduated in the year 2020. My research interest includes analog/mixed-signal design and hardware security. I am currently working on the vulnerabilities associated with the analog domain and how to enhance their security compared to the digital environment, which has already received much attention in this regard.

Experience

  • Staff Engineer at Synopsys Inc
    Jun 2025 - Present · 1 yr 1 mo

    GenAI for Design Verification

  • Technical Engineering Intern at Synopsys Inc
    May 2024 - Aug 2024 · 4 mos

    LLM for Hardware Design with the R&D EDA-G team

  • Technical Engineering Intern at Synopsys Inc
    May 2023 - Aug 2023 · 4 mos

    ML Chip Design intern at R&D EDA-G

  • Summer Intern at SiFive
    May 2022 - Aug 2022 · 4 mos

    CPU Implementation with the Hardware Team

  • Research Internship at Technische Universität Berlin
    May 2019 - Jul 2019 · 3 mos

    Worked on the development of low power bandgap reference voltage using FDSOI MOSFETs for digital circuits.