Jie Wu

Chief Flash Architect at FutureWei Technologies

San Jose, California, United States

About

Experienced NAND/Storage System engineer

Experience

  • Chief Flash Architect at Huawei Technologies
    Jun 2015 - Mar 2018 · 2 yrs 10 mos

    Responsible for NAND Flash characterization for all Huawei’s Products at Corporate level, including Mobile applications, SSD applications and Storage applications. Bring up Huawei’s NAND Flash technical capability single-handed to be the leading one in China. Leader of media application lab in Huawei Central R&D, working on all NAND Flash memory including both 2D and 3D NAND(MLC and TLC), as well as emerging memory such as 3D Xpoint, from all memory vendors. Leader of technical team interfaces with memory vendors including Micron, Toshiba, and SK Hynix. Working with SSD controller team, mobile controller team on NAND Flash requirements. Define the NAND strategy with different product groups on SSD and mobile storage. Responsible for NAND reliability improvement through test mode retrim and characterization with test mode to improve the endurance and retention.

  • Architect(NAND Flash), ISSPI Office of CTO, at Toshiba America Electronic Components, Inc.
    Nov 2014 - Jun 2017 · 2 yrs 8 mos

    Improve NAND Flash quality and reliability for enterprise, hyperscale and clinet applications(both planar and 3D NAND). Expert in deployment of NAND Flash in enterprise storage solutions(SSDs, All Flash Arrays, SSD applications, etc). Maintain deep knowledge of techniques to improve NAND through test mode retrim and provide expert technical guidance for enhancing NAND characterization.

  • Principal Engineer at Skyera
    Jun 2013 - Nov 2014 · 1 yr 6 mos

    Own the NAND flash memory characterization on chips from multiple vendors with Most Advanced NAND(MAN), including Micron 20nm (L85A and C) and 16nm MLC (L95B); Toshiba 1Ynm MLC and TLC; Hynix 16nm MLC. Endurance/performance improvement through Test Mode commands and parameter retrimming, as well as data retention improvement to meet All Flash Array spec. Support NAND characterization on the development of LDPC ECC controller for the Latest process nodes.

  • NAND memory Technologist at HGST, a Western Digital company
    Jan 2013 - May 2013 · 5 mos

    Lead and own NAND characterization and qualification on Intel 20nm Flat-Cell NAND with 30K P/E cycling on 64Gb and 128Gb MLC chips(L84C and L85C) for enterprise PCI-e SSD card/drive, by using Test Mode(MLBi and MRR) commands to access 100+ parameters on chip to fine tune the NAND memory array behavior, based on reasonable ECC engine.

  • Senior Staff device engineer at SanDisk
    Jan 2008 - Jan 2013 · 5 yrs 1 mo

    Work on 24nm NAND device development. Latest projects: Own and finished NAND qualification on 24nm 64Gb MLC with 30K P/E cycling for PCI-e enterprise SSD card/drive with certain ECC engine up to UBER spec. Own and finished NAND qualification on 24nm 32Gb SLC with 150K P/E cycling for enterprise SAS SSD drive with BCH ECC engine.