Jaydeep Kulkarni

Integrated Circuit Researcher

Austin, Texas, United States

About

Jaydeep Kulkarni received a B.E. degree from the University of Pune, India, in 2002, an M. Tech degree from the Indian Institute of Science (IISc) in 2004, and a Ph.D. from Purdue University in 2009. From 2009 to 2017, he worked as a Research Scientist at Intel Circuit Research Lab in Hillsboro, OR. His research work at Intel has been recognized with seven Divisional Recognition Awards for successfully transferring memory circuit technology research into Intel's next-generation Microprocessor products. He is a tenured associate professor in the Department of Electrical and Computer Engineering and a fellow of the Silicon Labs Chair in Electrical Engineering at the University of Texas at Austin. Dr. Kulkarni has filed 40 patents, published two book chapters, and 160 papers in refereed journals and conferences. His research focuses on machine learning hardware accelerators, in-memory computing, emerging memory devices, circuits, DTCO/STCO for emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing. Dr. Kulkarni received the Best M. Tech Student award from IISc Bangalore, Intel Foundation Ph.D. fellowship award, Purdue ECE Outstanding Doctoral Dissertation Award, the IEEE Transactions on VLSI Systems Best Paper Award, the SRC Outstanding Industrial Liaison award, Micron Foundation Faculty Awards (thrice), Intel Rising Star Faculty Award, NSF CAREER Award, SRC Innovator Award, UT ECE Junior Faculty Excellence in Teaching Award, and IEEE JETCAS Best Associate Editor Award. Dr. Kulkarni has participated in technical program committees of the ISSCC, VLSI Symposium, CICC, ASSCC, DAC, ICCAD, ISLPED, AICAS, and VLSI Design conferences. He has served as a Distinguished Industrial Lecturer for the IEEE Circuits and Systems Society and a Distinguished IEEE Solid-State Circuits Society Lecturer. He has served as a TPC Co-Chair and General Co-Chair for the 2017 and 2018 ISLPED, respectively, and as a TPC Co-Chair for the 2023 VLSI Design Conference in India. He is an associate editor for IEEE Transactions on Circuits and Systems -I. He currently serves as a distinguished lecturer for the IEEE Electron Device Society. He is a fellow of IEEE.

Experience

  • Visiting Professor, Circuits Research at NVIDIA
    Jan 2026 - Present · 7 mos

  • The University of Texas at Austin (9 yrs)
    • Director, Circuit Research Lab
      Aug 2017 - Present · 9 yrs

      The mission of UT Austin's Circuit Research Lab is to conduct research focusing on Integrated Circuits and Systems. This includes machine learning and domain specific hardware accelerators, in-memory computing, digital, memory and power-management circuits, DTCO/STCO for emerging nano-devices, 2.5D/3D heterogeneous integration, advanced packaging, hardware security, and cryogenic and radiation-hardened circuits.

    • Associate Professor
      Sep 2023 - Present · 2 yrs 11 mos

      Associate Professor with Tenure, Research in Microelectronic devices, technology, and Integrated Circuit Designs, Semiconductor Workforce Development

    • Fellow of Silicon Labs Chair in Electrical Engineering
      Sep 2020 - Present · 5 yrs 11 mos

  • Technical Advisor at imec
    Feb 2024 - Present · 2 yrs 6 mos

  • Interim Executive Director of Advanced Packaging Design at Texas Institute for Electronics
    Jun 2025 - Dec 2025 · 7 mos

    Building 3D ICs and Microsystems- utilizing mixed-semiconductor materials, Developing process design kits (PDK), Assembly Design Kits(ADK), reference designs and EDA flows for TIE's advanced packaging technologies.

  • Patent Technical Expert Witness at Freelance
    Nov 2023 - Dec 2025 · 2 yrs 2 mos

    Technical expert in the areas related to Semiconductor Memories and Integrated Circuit Designs.