Los Angeles Metropolitan Area
Over 25 years in Engineering Management, SoC/ASIC Architecture, lead design, verification, implementation, and product release. I Possess decades of industry experience and achievement — chip lead and architecture for multiple high-volume ASICs (over $1B in revenue); manages budgets for Capex and Head Count; leads cross-functional and multinational teams; provides mission critical support to multimillion dollar M&As. Creates innovative ASIC flow solutions that optimize team performance, streamlines processes, and reduces costs/waste. Versed in ISO26262 automotive functional safety process. Agile-scrum development and start-up experience Select previous accomplishments include: *Led many large scale SoCs into high volume production *Repeatedly sought after and recruited to senior roles through my career *Well versed in many IP including Interface IP, Mixed Signal Design/SerDes, ARM CPU, AMBA and NOC interconnect, etc *Well versed in all areas of SoC/ASIC design flow including Architecture, MATLAB/C modeling, RTL design, UVM and Formal verification, Rule Checking, Synthesis, Static Timing, Formal Analysis, LBIST, Scan Compression, MBIST, Floorplanning, Clock Tree Synthesis, Placement, Routing, Physical Verification, Signal and Power Integrity, System Level Testing, ATE production testing, HTOL, DPPM reduction, and Failure Analysis *Flow improvements leading to reduced errors and shortest turn around times *Deep knowledge of the SoC architecture, design, implementation, and production processes down to 7nm * Tasked by Broadcom leadership to oversee M&A technical due diligence for a $15M+ merger; successfully negotiated full transfer of employees and employment agreements. LET’S CONNECT ▬▬▬▬▬▬▬▬▬▬▬▬▬▬ I welcome invitations. It would be a pleasure to hear from you!
Selected by Synopsys to maintain a key technical leadership role post-acquisition of the Broadcom Central Engineering IP team in 2017. Technical leader to almost every global SoC company. *Earned selection by Vice President to run key, new growth opportunity *Technical lead of all customer engagements to ensure each customer has an optimized solution. *Oversees technical aspect of projects including architecture, design, integration, DV, RTL to pre-GDS implementation, place and route and integration into customer SoCs *Architecting, writing documentation, writing scripts, and running unit testing for revised Integration flow including RTL standards, Automated Assembly, Automated Test Bench Generation, LINT, CDC/RDC, UVM verification, Placement Aware Synthesis, Constraint Generation and Verification, Structural Formal Checks, and UPF based low power flow *Driving flow development through Agile-scrum with intent to use this process for IP project development *Leading key design projects including MACsec engine, PCIe Switch, and L2 Ethernet switch *Leading DDR interface SoC for DARPA CHIPS program under the Electronics Resurgence Initiative *Added IP working knowledge to include DDR3, DDR3L, DDR4, DDR5, LPPDDR4, LPDDR4, LPDDR5, MACsec, Ethernet L2 switch, PCIe switch, PCIe G5, CCIX, USB3.2, HDMI2.0, DP 1.4, DP1.4, USB Alternate modes, various security IP, and automotive functional safety *Working in various design nodes including 28m, 22nm, 16nm, 14nm, 12nm, 10nm, and 7nm *Enhanced working knowledge of Synopsys tools including VCS NLP, Verdi, Design Compiler Graphical, DFTMAX, Spyglass, PrimeTime SI/ADV/PX, Tetramax, UPF, SMS/SHS, Synplicity, Formality, and ICC2 *Led training and mentoring within my team to ensure all engineers are Subject Matter Experts in protocol and tools, with continuous industry learning to maintain current market knowledge.