Jason Byun

About

EXPERTISE: (1) Process Integration of Semiconductor devices with diverse materials and devices, (2) Plan for Experience, Action, Data analysis, and Feedback to Improve/Solution (PADF) (3) Deep knowledges on Techniques/Processes/Materials, Device physics, and Analytical techniques, (4) Technical communication based on Data. Please see the attached resume for details

Experience

• Principal Product Engineer at Renesas Electronics
  Jul 2021 - Present · 5 yrs 1 mo

   Product engineering of BCD products  Foundry Technology

• Member of Technical Staff at onsemi
  Jan 2014 - Mar 2021 · 7 yrs 3 mos

   Achievements: 1) Successful development of BCD products (250 and 180nm with lower cost – called as BCDe, here “e” stands for economy) and its mass production. 2) Yield improvement for 90nm CMOS Image sensor. 3) Design and Planning for 40nm node BCDe  Contributions: 1) Process integration & Optimization of 250 and180nm BCD (FEOL and BEOL) 2) Test pattern design & Drawing (Layout) and Evaluation; Process control by Cp/Cpk

• Principal MTS at Analog Devices
  Feb 2011 - Feb 2014 · 3 yrs 1 mo

   Achievements: 1) Successful development of BCD products with 180 and 90nm nodes and its mass production  Contributions: 1) Process integration and optimization of 90nm BCD (FEOL & BEOL) 2) Test pattern/Process design, analysis, and optimization; Cp/Cpk control

• Process Integration Engineer at Aprina Imaging (ON Semi)
  Jun 2009 - Jan 2012 · 2 yrs 8 mos

   Achievements: 1) Successful development of CMOS Image sensor 90nm nodes and its mass production  Contributions: 1) Process Integration for FEOL & BEOL 2) Successful optimization of Low-k and Cu Interconnect 3) STI; Shallow Junctions; Gate/Capacitor dielectrics/electrodes; CoSi2; implantations in FEOL/MOL, etc

• Member of Technical Staff at Infineon Technologies
  Mar 2005 - Nov 2008 · 3 yrs 9 mos

   Achievements: 1) Successful development of 65nm CMOS/SRAM and mass production 2) Successful development of 65nm SONOS (NVM) and mass production 3) Successful development of MEMS  Contributions: 1) Image Shielding in CMOS Image Sensor: see Patent #19, 27, 28 2) Gate module in Non-volatile (SNOS) memories (NAND or NOR): see Patent #20-24 3) Gate Module in SRAM (65nm): see Patent #26 4) Strain engineering of STI and ILD in CMOS: Co-work with AMAT 5) Strain engineering with CESL: tensile strained PECVD-SiN (see Patent #25) 6) Process Integration for FEOL & BEOL: STI/Gate Module, and Salicide (CoSi and NiSi), BEOL