Boston, Massachusetts, United States
Currently, I am a Senior Silicon Design Engineer at AMD working on SoC RTL Integration. I am also currently pursuing my Masters in Computer Engineering at Northeastern University. I graduated Northeastern University in 2024 with a B.S. in Computer Engineering, minoring in Physics, with a strong background in hardware and software development. My primary interests include low level hardware design using HDL and embedded software design. I am self-motivated, driven, and can adapt to any challenge presented. I enjoy cooperative environments and have excellent communication skills.
- Design and integrate critical functional blocks on the SoC Integration taking design from bring-up to tape-out. - Cooperate with Physical Design (PD), Design Verification (DV), Design for Test (DFT), Architecture, and other RTL Design teams to make sure that area constraints, design goals, and timing requirements are met. - Lead chip-wide JTAG design and implementation in Verilog, conforming to IEEE standards, optimizing for power and timing, while collaborating with PD and DV teams for seamless integration. - Manage signal routing, retimers, channels, and other necessary System on Chip (SoC) aspects on the integration level. - Implement various tests to run Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Gate level simulations. - Developed RTL logic and architectural design in Verilog from bring-up to tape-out for multiple product lines. - Automated chip-wide signal routing, timing pipeline generation, and CDC module development using Python and Perl scripts, significantly improving engineering efficiency and reducing manual errors.
- Joined the Wireless and Digital Services division in developing an LTE WIFI network for commercial airplanes. - Addressed client design problems and requirements through programming in C, C++, and Rust in a WSL environment. - Built, debugged, and deployed Linux distributions using Yocto for the purpose of creating specialized operating systems. - Aided in early software and hardware prototyping of ROS and C++ based robots capable of real time obstacle avoidance
- Coded blocks in Verilog which are responsible for clock domain crossing between the processing unit and peripherals. - Designed a wrapper in Verilog for a client’s logic design in order to ensure functionality and incorporate it into the chip. - Received and accepted full time return offer for Digital IC Design Engineer position
-Design and implement firmware written in VHDL and C on FPGA based high-speed 8G and 12G systems. -Validate hardware and software by automating tests developed in SystemVerilog, Python, and C to ensure product reliability. -Create applications leveraging different storage interfaces, I2C, SPI, PCIe, IP, and peripheral devices to meet customer needs. -Collaborate with electrical, software, and firmware engineers in the interest of creating connected designs across disciplines. -Maintain a high level of documentation using SVN, diagrams, and thorough commenting assuring clear and concise code.