Washington DC-Baltimore Area
I am currently developing my skills in FPGA Application Design as an Application Engineer at Annapolis Micro Systems. I earned my M.S, Electrical and Computer Engineering from Georgia Tech in May 2024 after completing my B.S., Computer Engineering along with a minor in Computing & Intelligence in May 2023.
Worked at the Information and Communications Laboratory (ICL) at GTRI. Developed novel design, verification, and implementation of workflow for FPGA-in-the-loop system specializing in signal distortion cancellation from Frequency Selective Limiters (FSL). Delivered debugging system for RFNoC system to customer - utilizing system LED interfacing.
Worked with peers in Computer Engineering to develop a High Level Synthesis (HLS) debugging tool. This tool improved on designs by Vitis HLS (AMD) and helped improve debug times for FPGA developers