Taiwan
1. 802.3 ethernet serdes IP -USXGMII interface 2. MAC layer
1. USB 3.1 link layer sub module maintain & verification 2. USB 3.1 whole chip synthesis & STA
1. Tablet SoC whole chip integration, timing closure, system architecture planning 2. DFT/ATPG (scan chain insertion), Memory BIST circuit generation, work with test engineer for CP/FT test