Butterworth, Penang, Malaysia
SUMMARY OF PROFILE: * Goal-oriented individual with leadership abilities * Willing to work with and learn from staff at all levels * Fast learner and enthusiastic to pick up new skills and explore in new area Specialties: 1) Experience and have strong enthusiasm in semiconductor test and reliability engineering 2) Experience in 1st silicon debug characterization and verification, wafer sort and final test methodology, and reliability characterization on semiconductor devices 3) Proficient to utilize C/C# language and Python scripting in test automation, e.g. ATE test program 4) Experience in performing statistical commonality analysis and have strong enthusiasm in data science field Technical Referee/Reviewer for: 1. Springer’s Journal of Applied Phyiscs A 2. Elsevier’s Solid-State Electronics 3. IEEE Transactions on Electron Devices 4. Physical Science International Journal 5. IEEE IPFA conference
Led Intel MYS Sort & Burn-In Product Development Engineers (PDE) team in strategizing and delivering contents and test programs for sort and burn-in sockets to support NPI product roadmaps across diverse business units in Intel, e.g. client desktop/mobile, data center server, discrete graphics, AI accelerators, chipsets, custom ASIC microprocessors, etc. Manage and delivered critical product qualification burn-in solutions on Intel's knowledge based qual and Industry standard based qual methodologies that includes Early Life Fallout Rate (ELFR), Extended Life Time (ELT), High Temperature Operating Life (HTOL) etc. On Sort, manage and delivered critical high voltage stresses in sort test program and establish it as quality baseline/yield monitor for Intel's fab. Led the R&D effort in developing and implementing product sort & burn-in strategies to manage the backend yield and outgoing quality aligning to customers' quality, reliability and yield expectations. Collaborated with Intel's factories across the globe to ensure sort & burn-in strategies met the expected product health indicators' commitments by driving key decisions and tradeoffs that balance manufacturing yield and quality requirement. Drive, define and establish standardized requirements for design-for-test (DFT) and design-for-infant-mortality-stress (DFIMS) strategies during NPI product's technology readiness and product definition phase to align receivables and deliverables with all stakeholders, e.g. design, architect, test engineers etc. Drive and deliver smooth execution of 1st silicon power on validation and test program releases for both sort & burn-in sockets. Led long range and tactical planning cycles, e.g. headcount, expenses and capital forecasting to drive strategic operational efficiency. Partnered with various Intel business units to align forecasts with business objectives, drive and implemented cost control initiatives, resource optimization and organizational growth/scalability.
Technical individual contributor to support the product and technology startup and ramp to meet Quality and Reliability (Q&R) requirements. This involves qualification or certification on new product and/or process, implement monitors and drive effective excursion management and prevention through rigorous risk assessment with predictive analytics and machine learning knowledge (for example Statistical Bin Limit issues, Customer issues, factory excursions)
• Technical Lead for Reliability Engineering team in Motorola Solutions Malaysia that actively lead and/or contribute to the reliability initiatives that covers all Motorola Solutions Reliability Lab worldwide. Mentor and coach peers to publish reliability engineering technical paper in Motorola Technical Symposium, i.e. 1 paper as main author and 3 papers as co-author in Motorola Technical Symposium 2014.
Collaborate with Non-volatile Technology and Product Engineering teams worldwide in reliability research and development projects that aligns well to R&D roadmap of the company.
At Package level test and characterization: • Support product characterization and debugging to ensure the product meet data sheet specs. Perform product qualification to determine quality and reliability of product, and carry out failure analysis of excelsior rejects and implement corrective actions At Wafer level sort and characterization: • Establish wafer level capabilities in Penang for future product characterization and have the wafer level setup ready in Spansion PNG plant by end of Q4'07. Provide 24 hour coverage on wafer level debugging and characterizaton, and establish this capability in Spansion PNG plant for future product characterization by the end of Q4'07.