Round Lake, Illinois, United States
Instrumentation and Controls for a Neutron-Flux Detector sub-system : design of solid-state relays (break-before-make) controllers, current sensing control, I-V conversion control, ADC sampling control, and robust signal processing and communications links to a central master controller unit. Control and monitoring of Calibration, Run, I-V, and self-test modes of the detectors. Reconfigurable sequencer for auto-sampling of multiple ADC channels. Altera Cyclone-V and Quartus (Qsys, PlatformDesigner, SystemConsole). Avalon/AXI4-Stream implementations.
FPGA and ASIC systems for next generation avionics and GPS receivers. L1 C/A channel processing and Gold code and carrier measurements and optimizations. L2 CM/CL channel processing, CM/CL local code generation and zero-padding for code despreading of the received stream.
Versal-ACAP FPGA processors for high speed, high bandwidth sensor/detector arrays and RFIC applications. Completed a custom SystemVerilog architecture for ARM AXI4-Stream data link processing for Aurora 64b/66b multi-Gigabit Serdes optical transceiver links.
FPGA designs for medical CT, PET, and MRI scanners. High speed DMA channel architectures for data acquisition and data processing from medical scanner sub-systems. Defined and implemented the FPGA-side of several product features, including : + C/C++ HLS signal processing modules and implemented as signed fixed-point arithmetic with Vitis - Vivado for Ultrascale+ FPGAs. Applications to RF and Magnetic field sensing and control (MRI). + ARM GIC (Zynq MPSoC) interrupt controller interfaces for various interrupt sources (sensors) with multiple sample rates (MRI, CT, others). + Power Amplifier (PA) control+status interfaces over multiplexed data and address PA bus (MRI). + Start/stop scan control logic (pre-scan calibration) for scan preparation and configuration. Completed all of my milestones for new scanner features, enabling future SW development. + PCIe Gen3 x 8 endpoints with support for XDMA transfers to/from on-FPGA SRAM and to/from off-FPGA DRAM, under transfer constraints such as bandwidth, latency, and jitter. + Versal-ACAP Ethernet MRMAC node with packet generator for link loop-back testing. + Versal-ACAP AI-Engine graph (DSP filter) compiled for parallel processing in a 7-way VLIW SIMD architecture. + Completed ASIC Arbiter modules Formal verification with SystemVerilog Assertions (SVAs) in Cadence Jasper and in Synopsys VC-Formal.
+ Design and integration of a novel streaming LDPC encoder interface block for a 4G/5G (600,900) code with Zc=60. The interface is low-latency ( approx. 80 cycles ) between 16-bit wide SRAM and 600 bits at the encoder input bus. The same interface block is reconfigured to connect the encoder output (900 bits ) to 16-bit SRAM. + Contributed interface designs for a first successful LDPC link in a Canopy fixed wireless network. Implemented in Intel / Altera Cyclone V, Cyclone III and Quartus.