Sumerpur, Rajasthan, India
GPIO Interface Design (Cadence Virtuoso | TSMC 65nm, CMOS 22FDX) Designed 1.8V & 3.3V GPIO interfaces with 0.7V/1V core, focusing on schematic-level design, transistor sizing, and timing optimization. Developed receiver path (Schmitt Trigger, level shifters, buffer chain) and transmitter path (level shifters, pre-driver, driver stages). Implemented 2× architecture to enable 3.3V operation while ensuring 1.8V device reliability. Added Fail-Safe Circuits for robust protection under fault conditions. Verified complete AC/DC specifications across PVT corners, ensuring junction voltage protection and reliable performance.
• Processed the PicoRV32 Processor GitHub repository with all Verilog files and constraints. • Executed RTL to GDSII flow for PicoRV32 using OpenROAD with Nangate45 technology and optimized the design flow.