Tomasz Hemperek

ASIC Design Engineer | Physicist

Mülligen, Aargau, Switzerland

About

Full-stack hardware engineer with 15+ years of experience spanning device physics, ASIC/FPGA design, large-scale mixed-signal IC implementation, system-level integration and data analysis. Specialized in semiconductor pixel detectors for ionizing radiation. PhD in experimental particle physics. Led pixel-detector ASIC design for the ATLAS and CMS experiments at CERN’s LHC. Open-source enthusiast and Cocotb maintainer. 🔗 GitHub: https://github.com/themperek/ 📚 Publications: https://inspirehep.net/authors/1062108

Experience

  • DECTRIS Ltd. (Baden, Aargau, Switzerland)
    • Lead ASIC Engineer
      Jul 2025 - Present · 1 yr

    • Senior ASIC Engineer
      Sep 2022 - Jul 2025 · 2 yrs 11 mos

      Specializing in hybrid pixel sensor and ASIC technologies. Digital design - from system-level architecture to physical implementation - as well as mixed-signal verification and validation. Leading technology R&D projects focused on advanced X-ray and electron detection.

  • The University of Bonn (Full-time · 14 yrs 5 mos)
    • Scientist / ASIC Design Engineer
      Apr 2018 - Aug 2022 · 4 yrs 5 mos

      Research and development of silicon detectors and readout. - Lead Designer in multiple international ASIC projects (180-65nm) - New types of silicone sensor development. - Digital/RTL design (Verilog/SV) - Digital verification (Python/SV/UVM) - Digital/mixed full implementation and sign-off (Synopsys/Cadence) - DAQ development (Firmware/FPGA and software) - Analog design and verification (Virtuoso) - Data analysis (Python) - Semiconductor device simulation (Sentaurus) - EDA/PDK and computing infrastructure maintenance - Teaching: C++/Python/Electronics/ML for HEP - Student supervision (PhD, MSc)

    • ASIC Design Engineer / PhD
      Apr 2008 - Apr 2018 · 10 yrs 1 mo

      Specialized on pixel detectors, into a university based facility for detector instrumentation and associated front end electronics. IC development (mixed-signal) for semiconductor detectors from concept to testing. Process development for new sensor types. System administration and software support.

  • ASIC Design Consultant at Freelance
    Jul 2017 - Aug 2022 · 5 yrs 2 mos

    - RTL Design (Verilog, SystemVerilog) - Verification (SystemVerilog, Python) - EDA software and PDK support - Mixed/Digital Flow (DC Compiler, Genus, Innovous, Tempus, PrimeTime, ...) - Mixed/Analog Verification (Virusoso, ...) - DAQ development (Software, Firmware) - TCAD (Sentaurus)

  • Associate Software Engineer at Mentor Graphics Corporation
    Sep 2007 - Mar 2008 · 7 mos

    IC Packaging & RF software development. (C++/MFC)

  • Analog IC Design - Internship at Institut Pluridisciplinaire Hubert Curien (IPHC) - CNRS
    Feb 2007 - Aug 2007 · 7 mos

    Analog circuits design for CMOS vertex detector readout electronics.