Bengaluru, Karnataka, India
An accomplished Physical Design Engineer with close to 6 years of experience delivering high-performance silicon from RTL2GDS across 7+ tapeouts on advanced technology nodes. Proven expertise in leading end-to-end physical implementation for complex, high-frequency designs and subsystems with a focus on optimizing PPA by bridging the gap between RTL design and Physical Implementation.
Leading RTL2GDS physical design efforts for an in-house LPDDR6/5x/5 memory controller IP/subsystem, from synthesis and floorplanning through PnR to final signoff and tapeout
Secured Hardware Design for Approximate Circuits and VLSI Architecture for Novel Accuracy Configurable Approximate Multiplier • Designed a Logic Encryption based Technique for the Reconfigurable Approximate/Error tolerant circuits • Designed a novel accuracy reconfigurable approximate booth multiplier circuit with significant power savings upto 36% as compared to accurate multiplier circuit for the same accuracy.
Teaching Assistant for the laboratory classes of Introduction to Electronics and VLSI Engineering.
Engineered a custom H-tree for the CPU big core clock network, achieving a 25% improvement in latency and ensuring high-speed operation with minimal skew
• Designed complete data transfer of analog Partial Discharge signals from the XLPE cable to the processor by interfacing various hardware components like ADCs, DDR3 memory, clock synthesizer, processor, etc. with the Kintex7 FPGA, in order to detect the defects in the cable.