Taipei, Taipei City, Taiwan
As an experienced SRAM Compiler Design Engineer, I have developed a strong background in the semiconductor and electronics industries. I am well-versed in SRAM compiler design flow and possess in-depth knowledge of various memory scheme structures, including SP, OP, TP, DP, pseudo-TP, register file, and ROM. Throughout my career, I have gained experience in developing SRAM compilers across multiple technology nodes, such as 22nm, 20nm, 16nm, 7nm, and 5nm. I have also had the opportunity to collaborate with CAD teams to optimize SRAM automatic design flow, working on aspects such as QA, noise tolerant calculation, timing characterization, and power characterization. In my current role, I lead a team in the memory compiler department, where we focus on developing memory compilers and conducting PPA assessments before accepting projects. Additionally, I collaborate with Field Technical Support (FTS) teams to provide pre-sale and post-sale consultation services.