Greater Hyderabad Area
Experienced VLSI Frontend Engineer specializing in RTL Design, Functional Verification (SystemVerilog/UVM), Validation, and EDA Automation, with growing expertise in AI-driven engineering workflows and Generative AI applications for semiconductor design and verification. Currently working at Synopsys as a Senior Validation/Verification Engineer, contributing to advanced digital design and validation solutions using Verilog, SystemVerilog, and scalable verification methodologies. Passionate about building efficient, automation-first workflows that improve productivity, debug efficiency, and verification quality across complex frontend environments. My interests extend beyond traditional verification into the intersection of AI and VLSI — including LLM-powered automation, intelligent debugging, RAG-based engineering assistants, verification productivity tools, and AI-assisted design flows. I actively explore how Generative AI can transform RTL development, verification, documentation, and engineering knowledge systems. I enjoy solving challenging problems, optimizing workflows with Python and Shell scripting, and developing scalable tooling that accelerates design and verification cycles. Constantly learning, building, and experimenting with emerging technologies in both semiconductor engineering and AI systems. Core Skills: • RTL Design & Functional Verification • SystemVerilog | UVM | Verilog • VCS | Verdi | Debugging & Validation • AMBA Protocols: AXI | APB • Python | Shell Scripting | EDA Automation • AI for Verification & Engineering Productivity • Generative AI | RAG Pipelines | LLM Applications • Verification Automation & Workflow Optimization