Nuremberg, Bavaria, Germany
TECHNICAL LEADER – HIGH-SPEED ANALOG / ASIC DESIGN (OPTICAL INTERCONNECTS) Senior High-Speed Analog & ASIC Design Engineer with 9+ years of experience in CMOS and SiGe BiCMOS technologies, specializing in up to 112 Gbaud PAM4 optical transceivers and EPIC systems up to 3.2 Tbps. Proven track record of 11+ successful tape-outs, including multiple chip leadership roles, with full ownership from architecture definition to silicon bring-up and validation. Strong expertise in high-speed analog front-end design, transmission line optimization, and system-level integration in collaboration with firmware and lab teams. KEY ACHIEVEMENTS: • 11+ IC tape-outs across CMOS and SiGe BiCMOS technologies • 4+ chip leadership roles, including Tx macro ownership for high-speed optical transceivers • Delivered >100–112 Gbaud PAM4 links in EPIC systems up to 3.2 Tbps • Full lifecycle ownership: architecture → design → layout → silicon bring-up → validation • Proven record of first-time-right silicon in high-speed designs • Strong cross-functional collaboration with system, firmware, test, and lab teams • Experienced in translating system-level requirements into circuit-level implementations for high-speed optical links.
Application: Electronic-photonic integrated circuits (EPIC) for low cost electro-optical interconnects up to 3.2 Tera-bps; Projects: - DR 800 Gbps EPIC Transceiver: 8 parallel electro-optical interconnects operating at data rate 100 Gbps (53Gbaud PAM4); - DR/PCie 1.6 Tbps EPIC Transceiver: 16 parallel electro-optical interconnects operating at data rate 100 Gbps (53Gbaud PAM4); - DR/PCie 3.2 Tbps EPIC Transceiver: 16 parallel electro-optical interconnects operating at data rate 200 Gbps (112Gbaud PAM4); Main activities and responsibilities: - Technical Leader of the high speed Tx macro: architecture choice, feasibility and design of vga/ctle and driver; - Simulation and design of HS and Analog cirtuits in 45nm SOI-CMOS tecnology; - Assist in define the verification plan, develop testbench, write/debug test vectors to guarantee functionality and performance of the chip. - Drive and supervise the Layout floorplan of Analog/Digital/HS blocks; - Participate in scheduled tape-outs with consistent documentation of all designs and development activities; also focused on continuos improvement and development; - Design review and realize technical documentation; - Support chip level testing and debugging activities in the lab; - Assume technical lead role to guide and mentor junior design staff; - Guiding outsourced design teams; - Provide progress and status reports in a timely manner to supervisors and the management board.
Application: Electronic-photonic integrated circuits (EPIC) for low cost electro-optical interconnects up to 100-400 Gbps; EPIC for 77-GHz car radar. Projects: - PSM4 100 Gbps EPIC Transceiver with CDR: four parallel electro-optical interconnects operating at data rate 25.8 Gbps; - DR/LR1 100 Gbps EPIC Transceiver: one electro-optical interconnect operating at data rate 100 Gbps (53Gbaud PAM4); - DR/LR4 400 Gbps EPIC Transceiver: four parallel electro-optical interconnects operating at data rate 100 Gbps (53Gbaud PAM4); - EPIC for distributed radar sensors addressing autonomous self-driving applications. Main activities and responsibilities: - Simulation and design of RF/Analog and Digital cirtuits in SiGe BiCMOS tecnology; - Assist in define the verification plan, develop testbench, write/debug test vectors to guarantee functionality and performance of the chip. - Layout design of Analog/Digital blocks; - Work with chip leads to develop detailed and prioritized chip level design and layout workflow; - Participate in scheduled tape-outs with consistent documentation of all designs and development activities; also focused on continuos improvement and development; - Design review and realize technical documentation; - Support chip level testing and debugging activities in the lab; - Provide progress and status reports in a timely manner to supervisors and the management board.
Applications: RF harvesting, RFID, Wireless Power Transfer Projects: - Short/Long range RF-powered Transceiver at UHF frequency. - Efficient bidirectional data comunication and Power transfer in a system with Galvanic Isolation. Main activities and responsibilities: - Simulation and Design of RF/Analog integrated circuits for galvanically isolated systems in CMOS/BCD tecnology; - EM simulation and design of integrated passives; - Organize work to ensure that project timescales and design targets are met; - Provide technical support regarding feasibility investigations; PUBLICATIONS AND ACKNOWLEDGMENT: [1] A. PARISI, E. RAGONESE, N. SPINA AND G. PALMISANO, "GALVANICALLY ISOLATED DC-DC CONVERTER USING A SINGLE ISOLATION TRANSFORMER FOR MULTI-CHANNEL COMMUNICATION," IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, JULY 2020. [2] G. PELLECCHIA, N. GRECO, G. PAPOTTO, A. FINOCCHIARO AND G. PALMISANO, "RF-POWERED TRANSCEIVERS FOR LONG AND SHORT RANGE COMMUNICATIONS", ASSOCIAZIONE SOCIETÀ ITALIANA DI ELETTRONICA (SIE), PALERMO, ITALY, JUNE 2017. Supervisor: Prof. Giuseppe Palmisano
EF (Education First) Malta, St. Julian’s – English intensive course
Thesis title: LDO chopper Regulator ultra-low power in CMOS technology, 110/110 cum laude Design and simulation of a low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier for a Power Management Unit of RF Energy Harvesting System in Wireless Sensor Network Applications. Supervisor: Prof. Giuseppe Palmisano Company Supervisor: Ing. Ranieri Guerra