George Fleming

Senior Principal Test Engineer

Santa Clara, California, United States

About

Experience

  • Senior Principal Test Engineer at SiTime
    Jan 2026 - Present · 6 mos

  • Senior Staff Test Architect at Renesas Electronics
    Jul 2024 - Jan 2026 · 1 yr 7 mos

    Lead development and deployment of semiconductor test systems, processes, and technologies.

  • Co-Founder at Simulate Test Systems
    May 2023 - Aug 2024 · 1 yr 4 mos

    We developed turnkey solutions to simulate semiconductor test platforms. Our solutions allow real-time validation of the electrical test solution through a combination of SPICE simulations and integrated static analysis reports. We also provided customized solutions for advanced Design-To-Test verification and consulted on verification IP that integrates with existing design verification testbenches in Cadence IC design environment. Renesas bought our technology and brought in our team in 2024.

  • Texas Instruments (Dallas/Fort Worth Area)
    • Test Engineer & Technologist (Member, Group Technical Staff)
      Jun 2018 - May 2023 · 5 yrs

      Chief architect and lead developer creating automation tools for the Cadence Design Environment using C#, C++, Verilog, System Verilog, Verilog AMS, Skill, and Python. These software solutions verify DFT in a virtual ATE environment pre-silicon using grounds up Design Verification custom environments and were leveraged by over 30 projects collectively totaling $1B+ in revenue. Acted as key point of contact and consultant working with over 15 product teams spanning multiple power and analog signal chain business units. Collaborated with Design, DV, and Systems teams to plan and develop test strategies and verification tests for LDOs, Voltage References, Buck, Buck/Boost, PMICs, Rad-hard ICs, Supervisors, Load Switches, Power-muxes, and High Side Switches. • Developed grounds up Probe and FT solutions for Linear Regulators and Switching Regulators – 4 projects • Performed test platform conversions to Eagle Test Platform – over 3 million in cost savings • Led the ATE Co-simulation global initiative and member of TI’s Cybersecurity team • Created globally referenced documentation for both DV and ATE best practices • Developed silicon qualification schedules and manage qualification executions • Resolved quality and production issues as they came up across our global factories • 1 Patent granted for ground current signaling method on ATE.

    • Design Verification Engineer
      Jun 2017 - Jun 2018 · 1 yr 1 mo

      • Performed mixed-signal design verification for several new products • Acted as mixed-signal design verification lead for one new product • Developed functional models in Verilog AMS • Worked with Xcelium automation tools to increase effectiveness and coverage • Wrote System Verilog Test scripts to cover wide range of system applications • Developed Spot fire templates for cross functional data correlation analysis

    • Product and Test Engineer
      May 2015 - Jun 2017 · 2 yrs 2 mos

      • Converted test programs for dozens of devices to Eagle Test Platforms • Developed silicon qualification schedules and managed qualification executions • Resolved large number of complex quality and production issues across TI global factories

  • Mathematics and Science Tutor at DCCCD
    Jan 2013 - May 2015 · 2 yrs 5 mos

    • Developed students' analysis skills and aiding them in applying those lessons to course material. • Provided students with invaluable one-on-one access for information on coursework questions. • Aided other tutors in problem solving for challenging curriculum. • Subjects included Chemistry, Physics, Calculus, Differential Equations, Linear Algebra, Control Systems, Programming, and other Engineering Topics