New Delhi, Delhi, India
Hi, I'm Gaurav Gangwar — a motivated and detail-oriented VLSI engineer currently pursuing an M.Tech in VLSI from IIIT Delhi. I have strong hands-on experience in both analog and digital circuit design, RTL-to-GDSII flow, and industry-standard EDA tools such as Cadence Virtuoso, Innovus, Eldo, NC-Verilog, Tempus, and the Skywater PDK. Throughout my academic journey, I’ve worked on a range of complex VLSI projects including strong-arm latch comparators, 6T-SRAM arrays, two-stage operational amplifiers, and Skywater-based standard cell design. My areas of interest include analog/mixed-signal circuit design, RTL design, physical design, STA, and ASIC verification. I'm passionate about solving real-world hardware problems and contributing to next-generation semiconductor technologies.
Subject - Signal and System, Basic Electronics,Digital Circuits and Research Methods