Austin, Texas, United States
Experienced and detail oriented engineer with extensive experience in EDA design and layout in the semiconductor industry with a current focus in software QA testing. Specialties: Cadence Design Systems (Virtuoso Layout Editor, Assurra), SKILL (Cadence proprietary coding language), Calibre (Mentor Graphics DRV verification), UNIX, Windows XP, CATS, Macintosh, MS Office, parametric test probe verification, technical writing, analysis & problem solving, technical support & documentation, applications programming, quality assurance testing
Non-profit group that raises money for breast cancer research.
QA process and customer support for a small startup devoted to developing software solutions that integrate the EDA environment with various PLM systems (Agile/Oracle, MatrixOne) Principal QA tester for software product release cycles, testing each release with five supported PLM systems Developed QA process procedures for testing software updates and releases of Perception Software’s EDAConnect software products reducing QA process cycle time Validated all software bug fixes and feature enhancements as well as custom script functionality Managed bug tracking system from issue submission, prioritization and engineer assignment through resolution and closure for all reported bugs Primary customer support contact who managed issue tracking and engineer assignment Created and maintained procedure documentation for QA process and customer support escalation increasing overall process efficiency
Member of small design team devoted to the development and maintenance of a web-based proprietary tool for device engineer end users to automate generation and documentation of test scribes for multiple CMOS technologies Developed and updated Relative Object Design (ROD) Cadence SKILL code to automate layout of test structure content and documentation improving overall cycle time Setup and maintained technology files and project libraries for multiple CMOS technologies Composed technical documentation and created graphic representations of test structure generators for on-line reference by engineer end users reducing time needed for individual training Interfaced with device and process engineers to establish test structure specifications and parametric variables for new test structures and feature enhancements to existing ones minimizing the need for multiple future edits Provided user training and system support to engineer end users Generated production and custom test scribes as needed
Performed manual CAD layout of test scribes, alignment keys and custom circuits as well as some scribe lane and test chip floorplanning for multiple CMOS process technologies Provided DRC verification and wavers of layout as well as modifications to DRC decks in accordance with design rule manuals and their revisions Reviewed and verified fractured data for mask prep, prepared photomask order paperwork and shipped photomask data to mask shop Generated complete test probe documentation for all test structures for production scribes as well as full characterization test chip vehicles Provided bench verification of test probe parametric data for multiple CMOS technologies as needed
Primary Point Of Sale (POS) system technical support for 13 stores nationwide Analyzed and administered hardware and software support calls for UNIX based POS system Developed and implemented hardware maintenance procedures expediting repairs and supply replacement components to stores Supervised and assisted in pre-electrical, communications cabling and POS system installation Provided POS system training for employees at all stores