La Penne-sur-Huveaune, Provence-Alpes-Côte d'Azur, France
Principal Senior Member of Technical Staff Analog/RF R&D Technologies Process Integration Manager Founder & Head of BSI (Brainstorming Service for Innovation, creativity center) Coach in creativity & Lateral thinking Strong scientist professional with an Engineer's Degree specialized in Materials Engineering and Semiconductors from Greenwich University and Polytech'Grenoble. Experienced R&D technologist on e-NVM CMOS & Analog/RF Technology development for Industrial, Secure, Automotive, Medical applications, in several countries (UK, USA, Italy, France), on 180, 130, 90, 40 & 28nm nodes. Skilled in Materials Physics, Semiconductor Physics, devices process integration, root cause analysis, data crunching and Creative Thinking for innovation and problem solving. PhD Supervisor and Trainer (CMOS Technology, Data Analysis, Creativity). Internal Coach in creativity, questioning, brainstorming and creative thinking techniques. Founder and Head of BSI (Brainstorming Service for Innovation). Coach in innovation projects through Design Thinking. Ideation Campaign Manager
Principal Senior Member of Technical Staff. Strong scientist professional with an Engineer's Degree specialized in Materials Engineering and Semiconductors from Greenwich University and Polytech'Grenoble. Experienced R&D technologist with a demonstrated history of working on e-NVM CMOS Technology for Industrial, Secure, Automotive and Medical applications. Leading Technology development or specific program at process integration level, on 180, 130, 90, 40, 28nm nodes. Skilled ++ in Root Cause Analysis, data crunching, Materials Physics, CMOS and creativity techniques. PhD Supervisor and Trainer (CMOS, creativity, Analyst). Internal Coach in creativity, questioning, brainstorming and creative thinking techniques. Founder and responsible of BSI (Brainstorming Service for Innovation). Internal coach in innovation project with Design Thinking. Ideation Campaign Manager for R&D Group.
8 inch Fab start-up: engineer and responsible of RTP/RTO/SACVD/LaserMarking processes development & qualification for 1st CMOS technology installation and qualification in the Fab. Process Development, transfer, industrialization and monitoring improvement Trained people and operators on processes, specifications and procedures, installed knowledge sharing sessions
New Processes development on SACVD for FLASH applications, development, qualification and industrialization SACVD, HDP and PE-CVD processes development
R&D Process Engineer in Dielectrics deposition area, responsible of SACVD process development, study of new dielectrics characteristics (gap filling capability, resistance to ageing, RI, manufacturability, ...) and their integration and qualification for Flash embedded technology roadmap
Study of LPCVD TEOS process capability - statistical study of different TEOS deposition recipes (DOE approach)
Study of the pyrophoric behavior of zirconium and zircaloy with nitric acid influence – confidential