Franck Gardic

IP/Integration Digital Verification Engineer at STMicroelectronics

France

About

Experience

  • STMicroelectronics (Crolles, Auvergne-Rhône-Alpes, France)
    • IP/Integration Digital Verification Engineer
      Jun 2015 - Present · 11 yrs 2 mos

      IP & Integration Digital Verification based on SystemVerilog/UVM software driven methodology, on NFC products families : - Test plan build up. - Python scripts driven test generation for IP tests generation. - IP/Integration tests generation/debug for test coverage, - Yield improvement tracking, design debug.

    • Digital Verification Engineer, Network On Chips
      Jan 2013 - Jun 2015 · 2 yrs 6 mos

      Specman based Digital Verification of Networks On Chips.

    • HW Design Project Manager
      Jun 2008 - Dec 2012 · 4 yrs 7 mos

      Qualification Testchips definition. CAD versus Silicon correlation. Product / Platform qualification yield detractor analysis. Task force leader.

  • Product/Test Engineer, silicon validation. at FREESCALE SEMICONDUCTEURS FRANCE SAS
    Jun 2006 - Jun 2008 · 2 yrs 1 mo

    - 65 Mbit eDRAM & 80 Mbit, dual BIST eDRAM tests programs build-up. - Characterizations of Test vehicles dedicated to new cells evaluations.

  • Altis Semiconductor (Corbeil-Essonnes, Île-de-France, France)
    • Final Wafer Test Engineering Support
      Jan 2005 - Jun 2005 · 6 mos

      FLASH memories, Final Wafer Test Support.

    • MRAM Project, Functional test and Characterization Engineer.
      Jan 2003 - Jun 2005 · 2 yrs 6 mos

      Definition of material (testers, probers, other equipments), and software needs. Coordination of test infrastructures setup (equipments, softwares, test sequence, datalogging in database). Test and Characterization programs build-up.

    • Technical leader of Product Engineering department.
      Jan 2003 - Dec 2003 · 1 yr

  • Product Test Engineer at IBM
    Dec 1996 - Dec 1999 · 3 yrs 1 mo

    Electrical characterizations of DRAM & SDRAM memories : - Test and characterization support of Final Wafer Test, Reliability, Characterization and Failure Analysis departments. - Optimization of wafer, prefuse, postfuse and module tests. Assignment (March - August 1997), IBM Burlington plant (VERMONT, USA) : transfer of 64 Mbit DRAM memory to Corbeil-Essonnes site.