Bavaria, Germany
Working in a group specialized in the design of monitor circuits and technology scouting: - Design of a synthesizeable hard IP to monitor the on-die supply voltage and aging Analysis and simulation of the supply voltage stability of a system-on-chip (SoC) - Developed implementation flow for fast exploration of design trade-offs - Design of a digital-to-timeconverter, as a building block for digital frequency synthesis - Implementation of a SoC power model to investigate technology scaling effects - Definition of stress tests to investigate aging effects; results were used to define an aging adder for the first wave of 28nm products - Leading of contingent workers
Research: Analysis of the degradation of digital integrated circuits due to aging effects (Industry partner Infineon Technologies AG): - Investigated impact of aging effects on timing and power consumption of logical and sequential standard cells - Developed (prototypical) tool for aging analysis on gate- and macro-level Teaching: - “Mathematical Methods of Information Technology” - “Seminar on Topics in Integrated System Design”