Sunnyvale, California, United States
• Defined our strategic platform build plan, ensuring high platform confidence on day-1 silicon bring-up and enabling fast-following application boards for customers, all while minimizing the total number of builds. • Performed market research and collaborated with silicon architecture, packaging, and mechanical/thermal to ensure future silicon will meet platform needs across a robust variety of potential products. • Architected, designed, and validated bring-up boards for the test chip and the main product silicon, emphasizing remote control and debug for our global team. Wrote extensive documentation on usage and software requirements. • Successfully drove silicon first-light in the lab, managed DUT rollout to the wider team, and kept lab machine condition and access carefully documented and maintained. Assisted silicon validation and debug. • Collaborated with firmware team to design the DUT control systems, participating in design meetings, contributing patches, and performing code reviews. • Built a novel, efficient, state-of-the-art board design stack by mixing KiCad for schematic capture with Cadence Allegro for layout design, tracking changes and ECOs via git, and enabling CI/CD for automated correctness checks and HTML schematic rendering. Wrote the style guide and best practices documentation. • Crafted labor-saving tools across multiple disciplines (package pinout, program scheduling, feedback management, schematic part creation, chip and board tracking, etc). • Oversaw three lab build-outs, creating floorplans, working with vendors, and sourcing materials and equipment. • Recruited and managed a team of 4 full-time and hosted 3 interns. Led cross-functional meetings and collaborated extensively across the company.
Designed and debugged complete system circuitry for next-gen Intel and ARM processors, including experimental SoCs, with a focus on reducing cost, scaling across many ODMs and OEMs, enabling flexibility and multi-sourcing, and landing advanced Type-C features with novel architectures. Worked extensively with firmware and kernel teams when designing and debugging hardware. Designed and took to production a cost-sensitive but high-performance 2-layer trackpad. On the software side, created crouton, a set of scripts to build and run graphical Debian-based chroots on Chromium OS, exceeding 40,000 downloads a month and maintaining a strong community of contributors. Revamped the CAD software infrastructure, scaled the group’s git usage to support many projects and teams, reverse-engineered CAD formats, and created HTML tools for viewing, diffing and merging schematic designs, greatly enhancing engineering productivity across Google. Highly involved in early USB-C spec work: designed and drafted major portions of the USB Type-C and Power Delivery 2.0 specs, representing Google’s interests across Android and Chrome in the USB-IF working groups. Designed Type-C bring-up boards that successfully predicted and kept ahead of spec developments. Designed hardware and built up a supply chain for Twinkie, an open-source USB-PD sniffer. Created strong relationships across the industry to interop and debug prototype Type-C devices. Negotiated pricing and advised IC roadmaps and architectures for USB-C and battery charging.
Developed the next version of a major product. On the hardware side, revamped the power tree with custom, inexpensive switching regulator layouts, laid out and escaped deep BGAs under extremely tight space constraints, routed 5 Gbps signal lines, and designed a custom external electrical interconnect using low-cost commodity connectors. On the software side, developed the firmware for a prerelease (still buggy) 32-bit ARM-based microcontroller, and adapted the host software to transparently support the old and new versions of the product.
Implemented and verified the power sequencing on a data center server platform. Created software for safe, in-system upgrading of power sequencer and other programmable parts. Leveraged the unique hardware implementation to create the equivalent of an AC power-cycle after a clean shutdown so system can be upgraded without human intervention in the data center. Performed voltage margining and a variety of failure analyses.