Stanford, California, United States
At the University of California, Berkeley, as a member of the Pilawa Group, I am researching the application of flying-capacitor multilevel converters for electrified transportation—work that holds a second meaning to me because of my lifelong interest in the outdoors and conservation. Developing myself as a power electronics engineer and shaping a meaningful career are both deeply important to me.
Served as a course assistant for EE 101B, Stanford's secondary circuits class from March 2024 to June 2024. Served as the head course assistant for EE 101A, Stanford's introductory circuits class from January 2024-March 2024.
To explore power distribution and electrical research at a governmental scale, I joined the National Renewable Energy Lab in the summer of 2023. Working under Gab-Su Seo, I derived a theoretical thermal model for a 500 kVa grid-connected inverter and researched the feasibility of controlling the thermal breakdown time in the event of ground faults through a combination of heatsink geometry, fan speed, and controlled ambient temperature.
Served as the head course assistant for EE 101A, Stanford's introductory circuits class.
Pursuing my current interest in power electronics, I worked for Airity Technologies after my junior year on the verification and testing of a multi-stage resonant converter topology. In this role, I completed the bring-up and characterization of output voltage for the company's first produced unit of a 7-stage Class-E inverter. In the process, I also improved the ADC calibration time by 5x. Since this was the first produced unit, I wrote detailed documentation of testing processes for internal use. In this role, I: ● Debugged inverter and rectifier stages with bench tools. Identified and fixed high-pass filtering parasitics in feedback path and identified and characterized high-frequency noise causing FTDI chip disconnection. ● Wrote Python scripts and contributed key functions to existing scripts to implement fault testing, finite state machine testing, feedback sensor calibration, open and closed loop operation, and PID parameter testing. ● Worked with software engineers to identify firmware bugs and determine optimal fixes. Identified one bug critical to correct operation of board: misconversion of parameters between non-volatile RAM and cache. ● Reworked board; regularly soldered and desoldered 0402 components and variety of IC packages. ● Prepared board for use in high-voltage environment using silicon conformal coating, corona dope, and galden. In addition, I designed and laid out a capacitive-coupled rectifier for a separate isolated resonant converter topology. ● Designed capacitive-coupled rectifier with buck regulator to generate isolated 5V supply for feedback side IC's. Completed initial layout for this design, handed off project at end of internship.