Dionísio Carvalho, Ph.D., MBA

Senior Physical Design Engineer | Team Manager at Semidynamics

Barcelona, Catalonia, Spain

About

Ph.D. in Electrical Engineering from the University of São Paulo ( Poli-USP) with 10+ years of experience in design, implementation, measurements, and tests of circuits and systems. MBA accomplished also from the University of São Paulo ( PECE-POLI). Ability to work on multiple projects simultaneously under pressure, strong technical aptitude, and excellent communication skills. I am currently a Senior Physical Designer and Product Owner, working with the 3nm technology node for complex AI SoC processor.

Experience

  • Semidynamics ()
    • Team Manager
      Jun 2026 - Present · 2 mos

    • Senior Physical Design Engineer
      Jun 2024 - Present · 2 yrs 2 mos

      Member of a team that successfully delivered a complex high-performance SoC tapeout on TSMC 3nm (N3P) process technology. - UCIe, SerDes and PLL IPs integration - Fusion Compiler flow from RTL to GDS - Primetime timing analysis - Redhawk-sc power analysis - Calibre DRC, LVS and Perc

    • Product owner
      Jan 2026 - Jun 2026 · 6 mos

      Product Owner using Agile ( scrum and kanban) methodology and Jira tool. - Backlog refinement - Hierarchy and team management - Resource allocation - Project status tracking - Stakeholders reporting

  • Digital IC Designer at Chipus Microelectronics
    Apr 2021 - May 2024 · 3 yrs 2 mos

    • Focused on ASIC backend flow, acting in the analog environment: Virtuoso, Calibre DRC and LVS, CDL import, VerilogIn schematic generation, Device Map development, Memory liberty file generation, etc; • Experience with: - Whole Cadence backend flow, including Genus; Innovus, Tempus, and Voltus; - Whole Synopsys backend flow, including DC, ICC2, FM, StarRC, and PrimeTime; - Freeze silicon ECO flow; • Elected to CIPA (2022).

  • Researcher PHD Student at CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
    May 2019 - Nov 2023 · 4 yrs 7 mos

    Program PROEX (Programa de Excelência Acadêmica ) from CAPES. Thesis title: Assessment of a software-defined radio aiming at microwave breast cancer detection. Advisor: Prof. Dr. Wilhelmus Van Noije Research Field: Breast Cancer, Medical Imaging, Software Defined Radio, UWB - SFCW - Radar Publications: • ETCM - 2022 Synthetic Pulse based on SFCW Modulation: a Proposition for Microwave Imaging •Biomedical Signal Processing and Control - Elsevier- 2022 ( Co-author) Low-cost device for breast cancer screening: A dry setup IR-UWB proposal •MICPRO - Elsevier - 2021 Experimental evaluation of a Software-Defined Radio through a Breast Phantom aiming at Microwave Medical Imaging. • NORCAS - 2020 Software-Defined Radio Assessment for Microwave Imaging Breast Cancer Detection. • CBEB - 2020 Analysis of Breast Cancer Detection Based on Software-Defined Radio Technology Internship PAE (Programa de Aperfeiçoamento de Ensino) - 09 -12/2020 : PSI3452-1 - Projeto de Circuitos Integrados Digitais e Analógicos working in Tanner design flow.

  • Hardware Test Engineer at LSI-USP
    Oct 2018 - Jun 2019 · 9 mos

    IC Test Leader working on the tests of the SAMPA version developed to Sphenix (BNL). - Test board production; - Components purchase; - Tests plan developments; - Physical tests and measurements; - Documentation and presentations. For project details: https://iopscience.iop.org/article/10.1088/1742-6596/1498/1/012025

  • Digital IC Engineer - SAMPA project - CERN/USP at LSI-USP
    Oct 2015 - Mar 2018 · 2 yrs 6 mos

    The LSI is developing an ASIC for the CERN calls SAMPA. The SAMPA is a new 32-channel front-end chip for the ALICE TPC and MCH upgrades designed in a 130nm CMOS technology with 1.25V nominal supply voltage. Each channel is composed of a charge sensitive amplifier, a semi-Gaussian shaper, a 10-bit ADC digital filtering DSP and a compression circuitry. The chip was approved by the CERN and is on mass production stage. I am engaged in the ASIC Digital blocks perfoming: - Scripts development for RTL compiler, Conformal and Encounter (EDI) ; - Backend flow of digital blocks using Innovus - Cadence; - Development of tests for SAMPA ASIC (DFT and Encounter Test); - FPGA-Sockit development for tests and DFT usage; - Physical tests and measurements; - Documentation and presentations.