Nijmegen, Gelderland, Netherlands
More than 25 years experience in Microelectronics: - FPGA Xilinx Vivado - ngspice - RTL hardware coding (VHDL/Verilog) - RTL Verification - DFT (Scan insertion) - Synthesis (Mixed Signal) - Logic Equivalence - Digital Place & Route - Static Timing Analysis - Analog backend RF/Power design - Mixed Signal design and View Generation - SoC integration - SDC Constraints - tcl perl python - EDA Keywords: Cadence, RTL, Verilog, IP Views, SoC EDI Innovus, virtuose, RF
Mixed Signal Design Engineer
RTL Design AMSIP Mixed Signal View Generation; Charaterization of AMSIP (SiliconSmart) TopLevel integration FrontEnd CPF Aware Synthesis (LP) Conformal Low Power PlaceAndRoute Initial design COMPELAB for Verification
IP View creation and validation for MSIP for integration in Digital Environment. Mixed Signal IP backend implementation & view creation. Digital Integration (P&R, PV, STA, Chip Finishing).
Analog RF C40 backend design