Union City, California, United States
Sr professional doing Architecture/Development/Application of ASICs in the Domain of Data Network (Physical to Application Layer) Career Summary: Architect/Micro-Architect, Technical Leader, Mentor, Advisor, Decision Maker: *Having worked, mentored & collaborated with 50+ strong design and verification team distributed over multiple locations an countries *Having started, advised, promoted multiple software companies to success *Having domain expertise in Network (Enterprise & Cloud) and FinTech *Having worked with Technologies of ASIC (5/7nm), SOC, FPGA *Having Designed Communication & Compute centric blocks & chips *Having protocol expertise in VirtIO, NVMe, Itch, Ouch, TCP/IP, Ethernet, PCI, AXI Flagship contribution: *Advising as board of SAAS software company in Construction & Governance Automation *Designed Low Latency, Low Power, High Speed (1.0+ GHz), High Bandwidth (400G) 512b wide datapath from Ethernet/ILA/PCIe back to Ethernet/ILA/PCIe doing hash, LPM and CAM searches *Micro-Architected & Implemented NASDAQ Book building & Order all in hardware *Founded, worked as CTO and merged CoVisible Pvt Ltd with a (now) public company *Eight US Patents granted Specialties/Skills: *Architecture: Requirement Analysis, Performance Modeling, Partitioning, Interface & API, Test Planning *Micro-architecture: Block Requirement Spec, Data Structures, Key Algorithms, Datapath, Error Injection *Technical Lead: Effort Estimation, Technical Guidance, Issue/AI Resolution & Tracking *Product Application/ Management: Interaction with Customers, AEs and Engrs; Product Knowledge Mgmt *Implementation: RTL, Test Bench, Synthesis, Simulation, Timing, Formal *Startup Experience: Member Founding team of 4 successful companies *Member BOD and BOA of software companies in the US and India *Protocol Suites: Ethernet, IP, TCP/UDP, PCIe, AXI, APB, IL/ILA, UART, SPI, I2C, MDIO, ITCH, OUCH, RASH; *Tools: MS-Office, MS Project, JIRA, VCS, SpyGlass, DCProto, PrimeTime, JIRA
Advising on various business functions
Micro-arch & RTL of IPs: Virtual Switch, Virtual IO Emulator (VEE), NVMe, ADC Calibration, FEC: Architecture handoff of IP, Micro-architecture (Block partitioning, Block requirement spec, Data structures, Key algorithms, Datapath, Performance, Power estimation, Error Injection spec), RTL (Code, Block test bench, Lint, Synthesis, Timing, Power). Backend support to Application Engineering.
Micro-Architect and RTL of Knowledge Based Processors, Smart NICs chips: Chip Micro-arch (Block partitioning, Block requirement spec, Data structures, Key algorithms, Datapath, Floor Plan, Performance, Power estimation, Error Injection spec), RTL (Code, Block test bench, Lint, Synthesis, Timing, Power). Backend support to Application Engineering.
Micro-Architect and RTL of Knowledge Based Processors: System Architecture handoff, Chip Micro-arch (Block partitioning, Block requirement spec, Data structures, Key algorithms, Datapath, Floor Plan, Performance, Power estimation, Error Injection spec), RTL (Code, Block test bench, Lint, Synthesis, Timing, Power).
Micro-Architect and RTL of Knowledge Based Processors: System Architecture handoff, Chip Micro-arch (Block partitioning, Block requirement spec, Data structures, Key algorithms, Datapath, Floor Plan, Performance, Power estimation, Error Injection spec), RTL (Code, Block test bench, Lint, Synthesis, Timing, Power).
I was involved in architecture, micro-architecture and back end interface of a 10M gate+ 10Mb memory grammar aware content processor chip. I also did application board architecture and testing (both RTL as well as board).
Cofounded the company. Architected company’s collaborative application server and worked with customers to understand the requirements and explain the features. CoVisible Solutions (India) has been merged with SoftTech Engineers.