David Westall

Process Engineer at Intel Corporation

Chandler, Arizona, United States

About

A well versed, hard-working, motivated individual with a long history of successful performance reviews. An independent contributor who possesses the ability to work successfully with cross-functional teams. Possesses significant technical experience gained while working for the leading semiconductor manufacturer in the world.. CAD design, project management, customer interface and sales. Specialties: Voice of the customer, process streamlining, Lean Six Sigma, Solidworks, MatLab, ANSYS and data analysis.

Experience

  • Intel Corporation (16 yrs 5 mos)
    • Manufacturing System Engineer
      Jun 2018 - Present · 8 yrs 1 mo

      Automation and Equipment Engineer responsible for factory equipment systems and automation development. Responsible to define and implement optimal WIP management practices such as Kan-Bans and etc. Support factory system readiness activities for equipment development to enable technology transfer to high volume sites for ramp. Proactively identify risks by conducting comprehensive FMEAs while responding to current events in order to achieve safety, quality, and output goals. Applying lean principles to systematically reduce waste and monetize the impact to the customer.

    • High Precision Maintenance Program Manager
      Jan 2017 - Jun 2018 · 1 yr 6 mos

      High Precision Maintenance Program Manager responsible for implementing Lean and High Precision Maintenance (HPM) systems within ATTD. Responsible for facilitating Kaizen and RIL events to save a combined 3,000 hours per year in equipment change over time.

    • Senior Litho Process Engineer
      Jun 2013 - Jan 2017 · 3 yrs 8 mos

      Tool and process owner in 14nm technology. Responsibilities include. 1. Yield improvement projects and root cause solutions to yield problems. 2. Tool availability, cycle time improvements and labor/cost reductions. 3. Tool and process sustaining, process control improvements, and process characterization. 4. Enhanced Availability of critical modules by implementation of LEAN & HPM (High Precision Manufacturing). 5. Work Content Reduction team (14nm process) by eliminating waste & streamlining operation.

  • Defect Metrology Engineer at intel
    2005 - 2009 · 4 yrs

  • Defect Metrology Intern at intel
    2002 - 2003 · 1 yr

  • Non Commissioned Officer at United States Marine Corp
    Nov 1995 - Nov 2000 · 5 yrs 1 mo