San Francisco Bay Area
Expert on ASIC design for test. TetraMAX, DFTMAX, fastscan, testkompress,ijtag, turboscan, virtualscan, VCS, NCverilog, Verilog, Formality/LEC. EDA development with C/C++, tcl/yacc/parser/swig/Qt. Interested in CUDA and parallel computing
Etching AI/LLM into ASIC. Led the architecture of a hybrid SSN/EDT flow, transforming DFT into a reusable, implementation-efficient solution. Drive full-chip integration, validation, and ATE bring-up. Focus on tsmc N2/N3 and 3D testing challenges.
SoC/ASIC integration. DFT team leader/architect -- make DFT reusable
3nm/5nm chip and 3D IC DFT
Broadband Communication Group SoC DFT
GPS/Wireless/Zigbee ASICs DFT tech lead. response all DFT features for ultra low power chips. scan synthesis, timing and DFT IPs. Implement test compression, memory BIST, Logic BIST, boundary scan, OCC, efuse, on-chip signal & clock monitor. Develop JTAG2ARM memory aceess and functional tests on ATE.