David Sherman

Principal Test Processing Software Engineer at Western Digital

Tustin, California, United States

About

Embedded Firmware design ° Complex Firmware / ASIC Bring-up ° Lab and development tool utilization – Bus Analyzers, Emulators’ ° FPGA Bring-up / RTL Verification ° ARM Micro Processor Family ° PowerPC ° ThreadX° Customer Support ° Firmware Design Specifications Innovative and resourceful Firmware engineer with a demonstrated record of achievement in the development of Embedded Firmware designs to work in an Engineering environment developing and deploying successful products to market. Highly experienced in developing embedded firmware. Proficient at resolving firmware issues utilizing emulators and other equipment necessary to design debug and support customer related firmware and hardware issues. Accomplished Firmware Engineer with the ability to collaborate effectively with all members of the organization to achieve business objectives. Guided the professional development of junior staff and expertly navigated a dynamic and constantly changing professional environment.

Experience

  • WD, a Western Digital company (15 yrs 2 mos)
    • Principal Engineer Software Developer
      Nov 2014 - Present · 11 yrs 9 mos

    • Staff VSC Firmware Engineer
      Jun 2011 - Present · 15 yrs 2 mos

      Develop and support all aspects of Vendor Specific Command processing. This entails support across all departments within the corporation, Controller, Servo, Channel and Process.

  • Principal Firmware Engineer at Western Digital
    Jun 2011 - Present · 15 yrs 2 mos

  • Principal Firmware Engineer at Emulex
    Feb 2002 - Apr 2011 · 9 yrs 3 mos

    Worked as an integral part of the Firmware Engineering team with significant experience solving development and customer problems. Responsibilities included Kernel development utilized in all of the Emulex Fibre Channel Host Bus Adapters. The firmware was written in both C and assembly language for the ARM family of microprocessors. My contributions at Emulex spanned several firmware disciplines. Specific areas of work included, although, were not limited to: Design and debug of the firmware for the 4, 8 and 16 gigabit per second Fibre Channel Host Bus Adapter. I led this development effort validating the new firmware in an FPGA environment prior to the tape-out and arrival of the ASIC. The FPGA was extremely important to the overall project success affording Emulex the ability to ship early prototypes to customers. The design involved converting from the ARM1136 to the ARM R4 microprocessor. I was responsible for modifying all of the firmware necessary to support this effort. This product was delivered to customers on time and is ranked superior to the equivalent product line produced by the Emulex competition.

  • Principal Engineer at Rainbow Technologies ° Irvine CA
    2001 - 2002 · 1 yr

    Cryptography

  • Sr. Principal Engineer at Western Digital
    1993 - 2001 · 8 yrs

    √ I was extensively involved in the Failure Analysis process in order to resolve system interface, cache and other firmware issues. Resolving failures required the use of oscilloscopes, logic analyzers, Nohau and Intel emulators. √ Encryption firmware for a Set Top Box designed by TiVo, utilized in the Audio Visual industry. This implementation provided a sophisticated drive locking mechanism needed to fulfill the customer’s requirements. √ The ATA 5 Password Security command set. Dell Computer specifically requested this firmware, with whom I work closely in order to manage their specific requirements. √ The Flash-programming algorithm utilizing the ATMEL and ST flash components. This firmware facilitated the reprogramming over the IDE interface of the flash component on the disk drives PCBA. As well as developing the flash-programming algorithm, I implemented the software on the host system utilized in transferring the hex file to the drive. √ I was a member of the Read Channel staff for 1-½ years. While I was a member of this group: √ I supported the Read Channel and Servo Channel optimization algorithms and developed special channel optimization algorithms for projects that involved the interface of different head/media combinations. √ I debugged MR head related micro-jog firmware as it related to the read-channel optimization process. √ I designed and implemented the interpolation firmware for the Read Channel optimization program utilized in the drive build process. This firmware reduced the manufacturing process by two hours. √ I designed and implemented the Shock Detection firmware utilized in the disk drive error recovery path. √ I developed a firmware algorithm to remove the MR heads from an (MR instability state.) This process improved yields in the factory by 2 percent. √ I designed and implemented the firmware for an Overlay Loader utilized in a new architecture.