Grenoble, Auvergne-Rhône-Alpes, France
Experienced in Physical Design (Backend section) Skills: + Physical Design experience for both Chiptop and Block level from RTL to GDSII. + Synthesize - optimize from RTL to Gate netlist. + Floor-planning, Timing optimization, CTS, Route and postRoute opt. + Using DC-G from Synopsys tool to optimize netlist and design with high density. + Knowledge and experience design skill for multi power/voltage domain (low power design). + Static Timing Analysis by PrimeTime. + Physical Verification by Calibre: DRC, Density, Antenna, LVS, LVL, ERC, ESD check. + IR drop/Power intergrity skill with Voltus. + Design skill for high-speed IP (1.6GHz and upper) to satisfy timing constraints and leakage power requirements. + Good analysis skill, optimization skill and debugging skill to solve timing violations, routing congestion and achieve high density design. + EDA tools: DC, ICCompiler, StarRC, PrimeTime, Formality, Calibre, Innovus, Tempus, Tweaker… Experience: + Good experience in Chiptop/Block/CPU IP Physical Design. + Joined in and taped out successfully several chips from MCU/CPU to SoC. + Well-experienced in 45nm, 40nm, 28nm, 16nm, 14nm GF, 12nm, 7nm, 6nm, 4nm, 3nm TSMC Foundry. + Ability to design high-speed, low-power, high-utilization CPU in layout such as: A7, A53... + Ability to debugging timing and CTS. Other + Good knowledge about Tcl, Awk + Good project planning, problem solving. + Well organized, self-motivated, and dynamic. + Good communication and team work skills. + Innovation mindset, workable under pressure individual as well as part of team + Flexible geographically. + Good at English and French: Both speaking and writing.
All aspect of layout design from RTL to GDS2: High speed CPU IP, Synthesis with DC or Genus, Place and Route with Innovus, PV (DRC, LVS, IRdrop, EM) with Calibre and STA with PrimeTime and Tweaker.
Design full flow from RTL to GDS2 IP Floor-planning, CTS, P&R, Timing optimization, STA, physical verification. CTS and Timing debugging. Flexibly work with Synopsys tools: IC Compiler I, II, StartRC, Primtime. Cadence tool: Encounter, Innovus, QRC, Tempus. Calibre DRC/LVS
- Characterize and simulate the VCOs (Voltage Controlled Oscillator) - Design its test structure in technology RFCMOS 0.13µm by Cadence. - Correlation report between simulation et measures in the lab.