Austin, Texas, United States
I am a dedicated product engineering leader with over 20 years of experience delivering exceptional AMD CPU products that push the boundaries of performance, energy efficiency, and innovation. My strong technical expertise, deep industry knowledge, and passion for mentoring and coaching enable me to successfully lead teams in developing industry-leading CPU solutions that serve a wide range of applications and markets. I value honesty, integrity, and loyalty, and strive to be a calm yet determined leader, continually seeking opportunities for personal and professional growth while making a lasting impact on AMD’s customers and the broader semiconductor industry.
Oversee the entire product development cycle, from concept to launch, ensuring high-quality solutions are delivered on time and within budget. Coach cross-functional engineering teams, clarify priorities, and drive accountability. Work closely with business, manufacturing, and supply chain partners to align product strategy with organizational goals, accelerate time to market, and maintain a culture of innovation, operational discipline, and excellence.
Manage a talented and highly skilled product engineering team. Responsible for yield, characterization, product definition, testing, quality, reliability, and volume production of semi-custom APUs.
Responsible for managing the quality and reliability of products throughout the entire product life cycle. Develops and executes qualification plans for new process/package technologies and new products, and establishes qualification strategies for test chips. Interacts with various foundries and assembly/test sites for vendor audits and qualification of new technologies.
Managed Intel’s Austin SoC quality and reliability team for smartphone and tablet application processors. The team was responsible for developing SoC qualification plans, ensuring products met quality and reliability (Q&R) targets, and executing qualification activities across multiple regions, including manufacturing and test sites in Asia, to demonstrate compliance with Q&R requirements.
• Through frequent customer engagement, he helped Intel customers eliminate technical barriers to platform releases. • Provided training to an engineering team comprised of junior and quality assurance engineers at Intel's global manufacturing sites. • Impact: Platform-level reliability path exploration helped reduce uncertainty between performance and reliability estimates in reliability modeling, thereby optimizing product yields and increasing Intel's profitability.
• Managed three engineers and a college intern on the 65nm microprocessor Q&R team. • Managed large projects across different organizations and delivered research related results. Responsible for assessment of key reliability limiters for Intel’s microprocessors including analyzing degradation data for intrinsic wear out modes and, through various computing tools, driving test setpoints and operating conditions to ensure all products meet Intel’s published reliability goals.