Sunnyvale, California, United States
Work experience in USA, Japan and Germany. My area of expertise is in physical design, custom circuit design, layout design and CAD scripting. I am have basic proficiency in logic design (Verilog). Recently I have worked mostly with automated CAD flows for logic synthesis and place&route, timing analysis, ECOs. I have worked on microprocessors such as the Emotion Engine (Playstation2, MIPS), Efficeon (x86), "Denver" (First X86, then ARM) and RISC-V. Specialties: Digital custom circuit design and ASIC design, timing, library cell design, clock tree design, signal and power integrity, power analysis, CAD scripting in Perl/Tcl.
Working on whatever gets thrown my way
- Helped debug "mysteries" found during silicon bring-up of ET-SoC-1 - Practiced soldering of mm-sized components under microscope - Taped out AI chip with >1000 CPUs and 28 B transistors in 7nm process - Maintaining CAD tool flows for DCG, RedHawkSC, PowerArtist, DPC (MMI) - Benchmarked ICC2 against Innovus against Aprisa - QA for standard cell library collateral - Timing and power comparison between Hspice and cell level tools such as PT/PX, DCG - Wire propagation delay studies - Studied viability of asynchronous NCL circuits at low voltage - Exploration of 7nm process at transistor level with Hspice looking for trends
- Worked on formerly secret "Project Denver" from the beginning - Led physical implementation of load/store unit and data cache control unit - Championed latch based design for the project - Set up daily regressions for selected CAD flows and filed hundreds of flow bugs - Timing closure in logic synthesis and layout (P&R) - Used Nvidia's proprietary ECO tool to close Data Cache Control timing for "Carmel" tapeout - Maintained scripts for generating wire delay tables for various processes - Benchmarked Genus against DCT - Analyzed and implemented fixes for IR drop violations
- Implement several blocks through automatic place&route (Talus) - Design floorplans for Multi-Core DSP (16 cores) in 65nm (TSMC) - Integrate DDR PHY and PCIE PHY IP into SOC - Participate in package design
- Custom design of complete fetch and scheduler data path and control logic, branch predictor - Working on global circuit implementation - Library cell design - Timing flow expert